diff options
author | Gabe Black <gabeblack@google.com> | 2018-11-19 18:14:16 -0800 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2019-01-31 11:02:05 +0000 |
commit | 5edfb67041ad1c246f4ceca147f06b9db3c0ecc3 (patch) | |
tree | 22cc08624db8bfa11e4ea7c9817a864ebc2ea706 /src/cpu | |
parent | 25474167e5b247d1b91fbf802c5b396a63ae705e (diff) | |
download | gem5-5edfb67041ad1c246f4ceca147f06b9db3c0ecc3.tar.xz |
arch: cpu: Rename *FloatRegBits* to *FloatReg*.
Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.
Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/checker/cpu.hh | 4 | ||||
-rw-r--r-- | src/cpu/checker/cpu_impl.hh | 6 | ||||
-rw-r--r-- | src/cpu/checker/thread_context.hh | 18 | ||||
-rw-r--r-- | src/cpu/kvm/x86_cpu.cc | 14 | ||||
-rw-r--r-- | src/cpu/minor/exec_context.hh | 10 | ||||
-rw-r--r-- | src/cpu/o3/cpu.cc | 16 | ||||
-rw-r--r-- | src/cpu/o3/cpu.hh | 8 | ||||
-rw-r--r-- | src/cpu/o3/dyn_inst.hh | 6 | ||||
-rw-r--r-- | src/cpu/o3/regfile.hh | 4 | ||||
-rw-r--r-- | src/cpu/o3/thread_context.hh | 16 | ||||
-rw-r--r-- | src/cpu/o3/thread_context_impl.hh | 8 | ||||
-rw-r--r-- | src/cpu/simple/base.cc | 2 | ||||
-rw-r--r-- | src/cpu/simple/exec_context.hh | 4 | ||||
-rw-r--r-- | src/cpu/simple_thread.hh | 12 | ||||
-rw-r--r-- | src/cpu/thread_context.cc | 8 | ||||
-rw-r--r-- | src/cpu/thread_context.hh | 24 |
16 files changed, 79 insertions, 81 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 9d6061ad8..30d17bdf6 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -199,7 +199,7 @@ class CheckerCPU : public BaseCPU, public ExecContext { const RegId& reg = si->srcRegIdx(idx); assert(reg.isFloatReg()); - return thread->readFloatRegBits(reg.index()); + return thread->readFloatReg(reg.index()); } /** @@ -374,7 +374,7 @@ class CheckerCPU : public BaseCPU, public ExecContext { const RegId& reg = si->destRegIdx(idx); assert(reg.isFloatReg()); - thread->setFloatRegBits(reg.index(), val); + thread->setFloatReg(reg.index(), val); setScalarResult(val); } diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index f6c35439b..86f022d41 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -208,7 +208,7 @@ Checker<Impl>::verify(const DynInstPtr &completed_inst) // maintain $r0 semantics thread->setIntReg(ZeroReg, 0); #if THE_ISA == ALPHA_ISA - thread->setFloatRegBits(ZeroReg, 0); + thread->setFloatReg(ZeroReg, 0); #endif // Check if any recent PC changes match up with anything we @@ -609,7 +609,7 @@ Checker<Impl>::copyResult(const DynInstPtr &inst, break; case FloatRegClass: panic_if(!mismatch_val.isScalar(), "Unexpected type of result"); - thread->setFloatRegBits(idx.index(), mismatch_val.asInteger()); + thread->setFloatReg(idx.index(), mismatch_val.asInteger()); break; case VecRegClass: panic_if(!mismatch_val.isVector(), "Unexpected type of result"); @@ -644,7 +644,7 @@ Checker<Impl>::copyResult(const DynInstPtr &inst, break; case FloatRegClass: panic_if(!res.isScalar(), "Unexpected type of result"); - thread->setFloatRegBits(idx.index(), res.asInteger()); + thread->setFloatReg(idx.index(), res.asInteger()); break; case VecRegClass: panic_if(!res.isVector(), "Unexpected type of result"); diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index 8ce5a740d..99506c1c8 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -209,9 +209,9 @@ class CheckerThreadContext : public ThreadContext RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); } RegVal - readFloatRegBits(int reg_idx) + readFloatReg(int reg_idx) { - return actualTC->readFloatRegBits(reg_idx); + return actualTC->readFloatReg(reg_idx); } const VecRegContainer& readVecReg(const RegId& reg) const @@ -280,10 +280,10 @@ class CheckerThreadContext : public ThreadContext } void - setFloatRegBits(int reg_idx, RegVal val) + setFloatReg(int reg_idx, RegVal val) { - actualTC->setFloatRegBits(reg_idx, val); - checkerTC->setFloatRegBits(reg_idx, val); + actualTC->setFloatReg(reg_idx, val); + checkerTC->setFloatReg(reg_idx, val); } void @@ -404,15 +404,15 @@ class CheckerThreadContext : public ThreadContext } RegVal - readFloatRegBitsFlat(int idx) + readFloatRegFlat(int idx) { - return actualTC->readFloatRegBitsFlat(idx); + return actualTC->readFloatRegFlat(idx); } void - setFloatRegBitsFlat(int idx, RegVal val) + setFloatRegFlat(int idx, RegVal val) { - actualTC->setFloatRegBitsFlat(idx, val); + actualTC->setFloatRegFlat(idx, val); } const VecRegContainer & diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc index 268fb9e6d..681e14200 100644 --- a/src/cpu/kvm/x86_cpu.cc +++ b/src/cpu/kvm/x86_cpu.cc @@ -838,7 +838,7 @@ updateKvmStateFPUCommon(ThreadContext *tc, T &fpu) for (int i = 0; i < 8; ++i) { const unsigned reg_idx((i + top) & 0x7); const double value(bitsToFloat64( - tc->readFloatRegBits(FLOATREG_FPR(reg_idx)))); + tc->readFloatReg(FLOATREG_FPR(reg_idx)))); DPRINTF(KvmContext, "Setting KVM FP reg %i (st[%i]) := %f\n", reg_idx, i, value); X86ISA::storeFloat80(fpu.fpr[i], value); @@ -848,9 +848,9 @@ updateKvmStateFPUCommon(ThreadContext *tc, T &fpu) for (int i = 0; i < 16; ++i) { *(uint64_t *)&fpu.xmm[i][0] = - tc->readFloatRegBits(FLOATREG_XMM_LOW(i)); + tc->readFloatReg(FLOATREG_XMM_LOW(i)); *(uint64_t *)&fpu.xmm[i][8] = - tc->readFloatRegBits(FLOATREG_XMM_HIGH(i)); + tc->readFloatReg(FLOATREG_XMM_HIGH(i)); } } @@ -1050,7 +1050,7 @@ updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu) const double value(X86ISA::loadFloat80(fpu.fpr[i])); DPRINTF(KvmContext, "Setting gem5 FP reg %i (st[%i]) := %f\n", reg_idx, i, value); - tc->setFloatRegBits(FLOATREG_FPR(reg_idx), floatToBits64(value)); + tc->setFloatReg(FLOATREG_FPR(reg_idx), floatToBits64(value)); } // TODO: We should update the MMX state @@ -1068,10 +1068,8 @@ updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu) tc->setMiscRegNoEffect(MISCREG_FOP, fpu.last_opcode); for (int i = 0; i < 16; ++i) { - tc->setFloatRegBits(FLOATREG_XMM_LOW(i), - *(uint64_t *)&fpu.xmm[i][0]); - tc->setFloatRegBits(FLOATREG_XMM_HIGH(i), - *(uint64_t *)&fpu.xmm[i][8]); + tc->setFloatReg(FLOATREG_XMM_LOW(i), *(uint64_t *)&fpu.xmm[i][0]); + tc->setFloatReg(FLOATREG_XMM_HIGH(i), *(uint64_t *)&fpu.xmm[i][8]); } } diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index 4cb67372e..051cf412c 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -99,7 +99,7 @@ class ExecContext : public ::ExecContext setPredicate(true); thread.setIntReg(TheISA::ZeroReg, 0); #if THE_ISA == ALPHA_ISA - thread.setFloatRegBits(TheISA::ZeroReg, 0); + thread.setFloatReg(TheISA::ZeroReg, 0); #endif } @@ -134,7 +134,7 @@ class ExecContext : public ::ExecContext { const RegId& reg = si->srcRegIdx(idx); assert(reg.isFloatReg()); - return thread.readFloatRegBits(reg.index()); + return thread.readFloatReg(reg.index()); } const TheISA::VecRegContainer & @@ -190,7 +190,7 @@ class ExecContext : public ::ExecContext { const RegId& reg = si->destRegIdx(idx); assert(reg.isFloatReg()); - thread.setFloatRegBits(reg.index(), val); + thread.setFloatReg(reg.index(), val); } void @@ -443,7 +443,7 @@ class ExecContext : public ::ExecContext return other_thread->readIntReg(reg.index()); break; case FloatRegClass: - return other_thread->readFloatRegBits(reg.index()); + return other_thread->readFloatReg(reg.index()); break; case MiscRegClass: return other_thread->readMiscReg(reg.index()); @@ -466,7 +466,7 @@ class ExecContext : public ::ExecContext return other_thread->setIntReg(reg.index(), val); break; case FloatRegClass: - return other_thread->setFloatRegBits(reg.index(), val); + return other_thread->setFloatReg(reg.index(), val); break; case MiscRegClass: return other_thread->setMiscReg(reg.index(), val); diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index ef3b17202..0cea74861 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1328,10 +1328,10 @@ FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg) template <class Impl> RegVal -FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg) +FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg) { fpRegfileReads++; - return regFile.readFloatRegBits(phys_reg); + return regFile.readFloatReg(phys_reg); } template <class Impl> @@ -1396,10 +1396,10 @@ FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val) template <class Impl> void -FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val) +FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, RegVal val) { fpRegfileWrites++; - regFile.setFloatRegBits(phys_reg, val); + regFile.setFloatReg(phys_reg, val); } template <class Impl> @@ -1448,13 +1448,13 @@ FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) template <class Impl> RegVal -FullO3CPU<Impl>::readArchFloatRegBits(int reg_idx, ThreadID tid) +FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) { fpRegfileReads++; PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( RegId(FloatRegClass, reg_idx)); - return regFile.readFloatRegBits(phys_reg); + return regFile.readFloatReg(phys_reg); } template <class Impl> @@ -1531,13 +1531,13 @@ FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid) template <class Impl> void -FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid) +FullO3CPU<Impl>::setArchFloatReg(int reg_idx, RegVal val, ThreadID tid) { fpRegfileWrites++; PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( RegId(FloatRegClass, reg_idx)); - regFile.setFloatRegBits(phys_reg, val); + regFile.setFloatReg(phys_reg, val); } template <class Impl> diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 30ed4ef3b..9612b3667 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -410,7 +410,7 @@ class FullO3CPU : public BaseO3CPU RegVal readIntReg(PhysRegIdPtr phys_reg); - RegVal readFloatRegBits(PhysRegIdPtr phys_reg); + RegVal readFloatReg(PhysRegIdPtr phys_reg); const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; @@ -467,7 +467,7 @@ class FullO3CPU : public BaseO3CPU void setIntReg(PhysRegIdPtr phys_reg, RegVal val); - void setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val); + void setFloatReg(PhysRegIdPtr phys_reg, RegVal val); void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); @@ -479,7 +479,7 @@ class FullO3CPU : public BaseO3CPU RegVal readArchIntReg(int reg_idx, ThreadID tid); - RegVal readArchFloatRegBits(int reg_idx, ThreadID tid); + RegVal readArchFloatReg(int reg_idx, ThreadID tid); const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; /** Read architectural vector register for modification. */ @@ -523,7 +523,7 @@ class FullO3CPU : public BaseO3CPU */ void setArchIntReg(int reg_idx, RegVal val, ThreadID tid); - void setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid); + void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid); void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, ThreadID tid); diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 9793f4ead..e6dffc81d 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -222,7 +222,7 @@ class BaseO3DynInst : public BaseDynInst<Impl> break; case FloatRegClass: this->setFloatRegOperandBits(this->staticInst.get(), idx, - this->cpu->readFloatRegBits(prev_phys_reg)); + this->cpu->readFloatReg(prev_phys_reg)); break; case VecRegClass: this->setVecRegOperand(this->staticInst.get(), idx, @@ -280,7 +280,7 @@ class BaseO3DynInst : public BaseDynInst<Impl> RegVal readFloatRegOperandBits(const StaticInst *si, int idx) { - return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); + return this->cpu->readFloatReg(this->_srcRegIdx[idx]); } const VecRegContainer& @@ -396,7 +396,7 @@ class BaseO3DynInst : public BaseDynInst<Impl> void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) { - this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); + this->cpu->setFloatReg(this->_destRegIdx[idx], val); BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); } diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 4077c99a4..163a13a25 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -194,7 +194,7 @@ class PhysRegFile } RegVal - readFloatRegBits(PhysRegIdPtr phys_reg) const + readFloatReg(PhysRegIdPtr phys_reg) const { assert(phys_reg->isFloatPhysReg()); @@ -316,7 +316,7 @@ class PhysRegFile } void - setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val) + setFloatReg(PhysRegIdPtr phys_reg, RegVal val) { assert(phys_reg->isFloatPhysReg()); diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 7858f5a0a..1ab1a0876 100644 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -189,10 +189,10 @@ class O3ThreadContext : public ThreadContext } virtual RegVal - readFloatRegBits(int reg_idx) + readFloatReg(int reg_idx) { - return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass, - reg_idx)).index()); + return readFloatRegFlat(flattenRegId(RegId(FloatRegClass, + reg_idx)).index()); } virtual const VecRegContainer & @@ -284,10 +284,10 @@ class O3ThreadContext : public ThreadContext } virtual void - setFloatRegBits(int reg_idx, RegVal val) + setFloatReg(int reg_idx, RegVal val) { - setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass, - reg_idx)).index(), val); + setFloatRegFlat(flattenRegId(RegId(FloatRegClass, + reg_idx)).index(), val); } virtual void @@ -391,8 +391,8 @@ class O3ThreadContext : public ThreadContext virtual RegVal readIntRegFlat(int idx); virtual void setIntRegFlat(int idx, RegVal val); - virtual RegVal readFloatRegBitsFlat(int idx); - virtual void setFloatRegBitsFlat(int idx, RegVal val); + virtual RegVal readFloatRegFlat(int idx); + virtual void setFloatRegFlat(int idx, RegVal val); virtual const VecRegContainer& readVecRegFlat(int idx) const; /** Read vector register operand for modification, flat indexing. */ diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 59562ba3b..2f653fa04 100644 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -205,9 +205,9 @@ O3ThreadContext<Impl>::readIntRegFlat(int reg_idx) template <class Impl> RegVal -O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx) +O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx) { - return cpu->readArchFloatRegBits(reg_idx, thread->threadId()); + return cpu->readArchFloatReg(reg_idx, thread->threadId()); } template <class Impl> @@ -264,9 +264,9 @@ O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val) template <class Impl> void -O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, RegVal val) +O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, RegVal val) { - cpu->setArchFloatRegBits(reg_idx, val, thread->threadId()); + cpu->setArchFloatReg(reg_idx, val, thread->threadId()); conditionalSquash(); } diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index c597ac904..f71277d1c 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -493,7 +493,7 @@ BaseSimpleCPU::preExecute() // maintain $r0 semantics thread->setIntReg(ZeroReg, 0); #if THE_ISA == ALPHA_ISA - thread->setFloatRegBits(ZeroReg, 0); + thread->setFloatReg(ZeroReg, 0); #endif // ALPHA_ISA // check for instruction-count-based events diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index d2107b89a..3090f38a0 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -202,7 +202,7 @@ class SimpleExecContext : public ExecContext { numFpRegReads++; const RegId& reg = si->srcRegIdx(idx); assert(reg.isFloatReg()); - return thread->readFloatRegBits(reg.index()); + return thread->readFloatReg(reg.index()); } /** Sets the bits of a floating point register of single width @@ -213,7 +213,7 @@ class SimpleExecContext : public ExecContext { numFpRegWrites++; const RegId& reg = si->destRegIdx(idx); assert(reg.isFloatReg()); - thread->setFloatRegBits(reg.index(), val); + thread->setFloatReg(reg.index(), val); } /** Reads a vector register. */ diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 00355c602..5c52ba28d 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -255,11 +255,11 @@ class SimpleThread : public ThreadState } RegVal - readFloatRegBits(int reg_idx) + readFloatReg(int reg_idx) { int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); - RegVal regVal(readFloatRegBitsFlat(flatIndex)); + RegVal regVal(readFloatRegFlat(flatIndex)); DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", reg_idx, flatIndex, regVal); return regVal; @@ -406,14 +406,14 @@ class SimpleThread : public ThreadState } void - setFloatRegBits(int reg_idx, RegVal val) + setFloatReg(int reg_idx, RegVal val) { int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); // XXX: Fix array out of bounds compiler error for gem5.fast // when checkercpu enabled if (flatIndex < TheISA::NumFloatRegs) - setFloatRegBitsFlat(flatIndex, val); + setFloatRegFlat(flatIndex, val); DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", reg_idx, flatIndex, val); } @@ -558,8 +558,8 @@ class SimpleThread : public ThreadState RegVal readIntRegFlat(int idx) { return intRegs[idx]; } void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; } - RegVal readFloatRegBitsFlat(int idx) { return floatRegs[idx]; } - void setFloatRegBitsFlat(int idx, RegVal val) { floatRegs[idx] = val; } + RegVal readFloatRegFlat(int idx) { return floatRegs[idx]; } + void setFloatRegFlat(int idx, RegVal val) { floatRegs[idx] = val; } const VecRegContainer & readVecRegFlat(const RegIndex& reg) const diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc index 7597dbfb2..3f5781b32 100644 --- a/src/cpu/thread_context.cc +++ b/src/cpu/thread_context.cc @@ -71,8 +71,8 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two) // Then loop through the floating point registers. for (int i = 0; i < TheISA::NumFloatRegs; ++i) { - RegVal t1 = one->readFloatRegBits(i); - RegVal t2 = two->readFloatRegBits(i); + RegVal t1 = one->readFloatReg(i); + RegVal t2 = two->readFloatReg(i); if (t1 != t2) panic("Float reg idx %d doesn't match, one: %#x, two: %#x", i, t1, t2); @@ -169,7 +169,7 @@ serialize(ThreadContext &tc, CheckpointOut &cp) RegVal floatRegs[NumFloatRegs]; for (int i = 0; i < NumFloatRegs; ++i) - floatRegs[i] = tc.readFloatRegBitsFlat(i); + floatRegs[i] = tc.readFloatRegFlat(i); // This is a bit ugly, but needed to maintain backwards // compatibility. arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs); @@ -213,7 +213,7 @@ unserialize(ThreadContext &tc, CheckpointIn &cp) // compatibility. arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs); for (int i = 0; i < NumFloatRegs; ++i) - tc.setFloatRegBitsFlat(i, floatRegs[i]); + tc.setFloatRegFlat(i, floatRegs[i]); std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs); UNSERIALIZE_CONTAINER(vecRegs); diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 6dde68650..098fe3bb2 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -208,7 +208,7 @@ class ThreadContext // virtual RegVal readIntReg(int reg_idx) = 0; - virtual RegVal readFloatRegBits(int reg_idx) = 0; + virtual RegVal readFloatReg(int reg_idx) = 0; virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0; virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0; @@ -252,7 +252,7 @@ class ThreadContext virtual void setIntReg(int reg_idx, RegVal val) = 0; - virtual void setFloatRegBits(int reg_idx, RegVal val) = 0; + virtual void setFloatReg(int reg_idx, RegVal val) = 0; virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0; @@ -338,8 +338,8 @@ class ThreadContext virtual RegVal readIntRegFlat(int idx) = 0; virtual void setIntRegFlat(int idx, RegVal val) = 0; - virtual RegVal readFloatRegBitsFlat(int idx) = 0; - virtual void setFloatRegBitsFlat(int idx, RegVal val) = 0; + virtual RegVal readFloatRegFlat(int idx) = 0; + virtual void setFloatRegFlat(int idx, RegVal val) = 0; virtual const VecRegContainer& readVecRegFlat(int idx) const = 0; virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0; @@ -467,8 +467,8 @@ class ProxyThreadContext : public ThreadContext RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); } - RegVal readFloatRegBits(int reg_idx) - { return actualTC->readFloatRegBits(reg_idx); } + RegVal readFloatReg(int reg_idx) + { return actualTC->readFloatReg(reg_idx); } const VecRegContainer& readVecReg(const RegId& reg) const { return actualTC->readVecReg(reg); } @@ -528,8 +528,8 @@ class ProxyThreadContext : public ThreadContext void setIntReg(int reg_idx, RegVal val) { actualTC->setIntReg(reg_idx, val); } - void setFloatRegBits(int reg_idx, RegVal val) - { actualTC->setFloatRegBits(reg_idx, val); } + void setFloatReg(int reg_idx, RegVal val) + { actualTC->setFloatReg(reg_idx, val); } void setVecReg(const RegId& reg, const VecRegContainer& val) { actualTC->setVecReg(reg, val); } @@ -590,11 +590,11 @@ class ProxyThreadContext : public ThreadContext void setIntRegFlat(int idx, RegVal val) { actualTC->setIntRegFlat(idx, val); } - RegVal readFloatRegBitsFlat(int idx) - { return actualTC->readFloatRegBitsFlat(idx); } + RegVal readFloatRegFlat(int idx) + { return actualTC->readFloatRegFlat(idx); } - void setFloatRegBitsFlat(int idx, RegVal val) - { actualTC->setFloatRegBitsFlat(idx, val); } + void setFloatRegFlat(int idx, RegVal val) + { actualTC->setFloatRegFlat(idx, val); } const VecRegContainer& readVecRegFlat(int id) const { return actualTC->readVecRegFlat(id); } |