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author | Andreas Sandberg <andreas.sandberg@arm.com> | 2019-01-26 09:19:22 +0000 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2019-02-22 10:47:36 +0000 |
commit | 7d71f6641fcb660de0f003e2c028b464d7116ca1 (patch) | |
tree | eab821617b26ce34b0dc834f2e0f11cfee67c2a0 /src/cpu | |
parent | 8e5d168332c4ac3851aee4f815cff0b62b37cc40 (diff) | |
download | gem5-7d71f6641fcb660de0f003e2c028b464d7116ca1.tar.xz |
python: Make iterator handling Python 3 compatible
Many functions that used to return lists (e.g., dict.items()) now
return iterators and their iterator counterparts (e.g.,
dict.iteritems()) have been removed. Switch calls to the Python 2.7
iterator methods to use the Python 3 equivalent and add explicit list
conversions where necessary.
Change-Id: I0c18114955af8f4932d81fb689a0adb939dafaba
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15992
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/BaseCPU.py | 16 | ||||
-rw-r--r-- | src/cpu/minor/MinorCPU.py | 2 |
2 files changed, 9 insertions, 9 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 007c869af..60c86a44f 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -241,26 +241,26 @@ class BaseCPU(MemObject): def createInterruptController(self): if buildEnv['TARGET_ISA'] == 'sparc': - self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)] + self.interrupts = [SparcInterrupts() for i in range(self.numThreads)] elif buildEnv['TARGET_ISA'] == 'alpha': - self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)] + self.interrupts = [AlphaInterrupts() for i in range(self.numThreads)] elif buildEnv['TARGET_ISA'] == 'x86': self.apic_clk_domain = DerivedClockDomain(clk_domain = Parent.clk_domain, clk_divider = 16) self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain, pio_addr=0x2000000000000000) - for i in xrange(self.numThreads)] + for i in range(self.numThreads)] _localApic = self.interrupts elif buildEnv['TARGET_ISA'] == 'mips': - self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)] + self.interrupts = [MipsInterrupts() for i in range(self.numThreads)] elif buildEnv['TARGET_ISA'] == 'arm': - self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)] + self.interrupts = [ArmInterrupts() for i in range(self.numThreads)] elif buildEnv['TARGET_ISA'] == 'power': - self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)] + self.interrupts = [PowerInterrupts() for i in range(self.numThreads)] elif buildEnv['TARGET_ISA'] == 'riscv': self.interrupts = \ - [RiscvInterrupts() for i in xrange(self.numThreads)] + [RiscvInterrupts() for i in range(self.numThreads)] else: print("Don't know what Interrupt Controller to use for ISA %s" % buildEnv['TARGET_ISA']) @@ -318,7 +318,7 @@ class BaseCPU(MemObject): # If no ISAs have been created, assume that the user wants the # default ISA. if len(self.isa) == 0: - self.isa = [ default_isa_class() for i in xrange(self.numThreads) ] + self.isa = [ default_isa_class() for i in range(self.numThreads) ] else: if len(self.isa) != int(self.numThreads): raise RuntimeError("Number of ISA instances doesn't " diff --git a/src/cpu/minor/MinorCPU.py b/src/cpu/minor/MinorCPU.py index bb4df82f0..ae97f6c4f 100644 --- a/src/cpu/minor/MinorCPU.py +++ b/src/cpu/minor/MinorCPU.py @@ -102,7 +102,7 @@ def minorMakeOpClassSet(op_classes): def boxOpClass(op_class): return MinorOpClass(opClass=op_class) - return MinorOpClassSet(opClasses=map(boxOpClass, op_classes)) + return MinorOpClassSet(opClasses=[ boxOpClass(o) for o in op_classes ]) class MinorFU(SimObject): type = 'MinorFU' |