diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-18 12:19:30 -0500 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-18 12:19:30 -0500 |
commit | 9e7dc343832f473b2058d4f9b39a27430142006f (patch) | |
tree | 5f61750159b2b3e64468155cb2d9a5d24a3d8524 /src/cpu | |
parent | c3ec52346b99d398916765679877686c109e3513 (diff) | |
parent | d19d7aa8a55cd4413ab00de69deb237d89d5ef4a (diff) | |
download | gem5-9e7dc343832f473b2058d4f9b39a27430142006f.tar.xz |
Merge zizzer.eecs.umich.edu:/.automount/zower/eecshome/m5/newmem
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/sparco3
--HG--
extra : convert_revision : f17800685609d8353ec14676f45fbb123fc4e6c3
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/o3/alpha/dyn_inst.hh | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index c340a806a..ee895d77c 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -123,6 +123,44 @@ class AlphaDynInst : public BaseDynInst<Impl> this->threadNumber); } + /** Reads a miscellaneous register. */ + TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) + { + return this->cpu->readMiscReg( + si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, + this->threadNumber); + } + + /** Reads a misc. register, including any side-effects the read + * might have as defined by the architecture. + */ + TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx) + { + return this->cpu->readMiscRegWithEffect( + si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, + this->threadNumber); + } + + /** Sets a misc. register. */ + void setMiscRegOperand(const StaticInst * si, int idx, const MiscReg &val) + { + this->instResult.integer = val; + return this->cpu->setMiscReg( + si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, + val, this->threadNumber); + } + + /** Sets a misc. register, including any side-effects the write + * might have as defined by the architecture. + */ + void setMiscRegOperandWithEffect(const StaticInst *si, int idx, + const MiscReg &val) + { + return this->cpu->setMiscRegWithEffect( + si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, + val, this->threadNumber); + } + #if FULL_SYSTEM /** Calls hardware return from error interrupt. */ Fault hwrei(); |