arch-arm,cpu: Add initial support for Arm SVE

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain <javier.setoain@arm.com>
- Gabor Dozsa <gabor.dozsa@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

7 files changed, 114 insertions, 18 deletions

diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py
index a408de3ab..21e37be87 100644
--- a/src/cpu/FuncUnit.py
+++ b/src/cpu/FuncUnit.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2010,2018 ARM Limited
+# Copyright (c) 2010, 2017-2018 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -47,13 +47,16 @@ class OpClass(Enum):
             'FloatMisc', 'FloatSqrt',
             'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
             'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
-            'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
-            'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult',
-            'SimdFloatMultAcc', 'SimdFloatSqrt',
+            'SimdDiv', 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu',
+            'SimdFloatCmp', 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc',
+            'SimdFloatMult', 'SimdFloatMultAcc', 'SimdFloatSqrt',
+            'SimdReduceAdd', 'SimdReduceAlu', 'SimdReduceCmp',
+            'SimdFloatReduceAdd', 'SimdFloatReduceCmp',
             'SimdAes', 'SimdAesMix', 'SimdSha1Hash', 'SimdSha1Hash2',
             'SimdSha256Hash', 'SimdSha256Hash2', 'SimdShaSigma2',
-            'SimdShaSigma3', 'MemRead', 'MemWrite',
-            'FloatMemRead', 'FloatMemWrite',
+            'SimdShaSigma3',
+            'SimdPredAlu',
+            'MemRead', 'MemWrite', 'FloatMemRead', 'FloatMemWrite',
             'IprAccess', 'InstPrefetch']
 
 class OpDesc(SimObject):
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index bbde89c00..a228893f2 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -118,7 +130,38 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
         }
 
         if (Debug::ExecResult && data_status != DataInvalid) {
-            ccprintf(outs, " D=%#018x", data.as_int);
+            switch (data_status) {
+              case DataVec:
+                {
+                    ccprintf(outs, " D=0x[");
+                    auto dv = data.as_vec->as<uint32_t>();
+                    for (int i = TheISA::VecRegSizeBytes / 4 - 1; i >= 0;
+                         i--) {
+                        ccprintf(outs, "%08x", dv[i]);
+                        if (i != 0) {
+                            ccprintf(outs, "_");
+                        }
+                    }
+                    ccprintf(outs, "]");
+                }
+                break;
+              case DataVecPred:
+                {
+                    ccprintf(outs, " D=0b[");
+                    auto pv = data.as_pred->as<uint8_t>();
+                    for (int i = TheISA::VecPredRegSizeBits - 1; i >= 0; i--) {
+                        ccprintf(outs, pv[i] ? "1" : "0");
+                        if (i != 0 && i % 4 == 0) {
+                            ccprintf(outs, "_");
+                        }
+                    }
+                    ccprintf(outs, "]");
+                }
+                break;
+              default:
+                ccprintf(outs, " D=%#018x", data.as_int);
+                break;
+            }
         }
 
         if (Debug::ExecEffAddr && getMemValid())
diff --git a/src/cpu/minor/MinorCPU.py b/src/cpu/minor/MinorCPU.py
index ae97f6c4f..5aebbf805 100644
--- a/src/cpu/minor/MinorCPU.py
+++ b/src/cpu/minor/MinorCPU.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2014,2018 ARM Limited
+# Copyright (c) 2012-2014, 2017-2018 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -148,15 +148,24 @@ class MinorDefaultFloatSimdFU(MinorFU):
         'FloatMultAcc', 'FloatDiv', 'FloatSqrt',
         'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
         'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
-        'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
+        'SimdDiv', 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
         'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult',
-        'SimdFloatMultAcc', 'SimdFloatSqrt', 'SimdAes', 'SimdAesMix',
+        'SimdFloatMultAcc', 'SimdFloatSqrt', 'SimdReduceAdd', 'SimdReduceAlu',
+        'SimdReduceCmp', 'SimdFloatReduceAdd', 'SimdFloatReduceCmp',
+        'SimdAes', 'SimdAesMix',
         'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash',
         'SimdSha256Hash2', 'SimdShaSigma2', 'SimdShaSigma3'])
+
     timings = [MinorFUTiming(description='FloatSimd',
         srcRegsRelativeLats=[2])]
     opLat = 6
 
+class MinorDefaultPredFU(MinorFU):
+    opClasses = minorMakeOpClassSet(['SimdPredAlu'])
+    timings = [MinorFUTiming(description="Pred",
+        srcRegsRelativeLats=[2])]
+    opLat = 3
+
 class MinorDefaultMemFU(MinorFU):
     opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead',
                                      'FloatMemWrite'])
@@ -171,8 +180,8 @@ class MinorDefaultMiscFU(MinorFU):
 class MinorDefaultFUPool(MinorFUPool):
     funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(),
         MinorDefaultIntMulFU(), MinorDefaultIntDivFU(),
-        MinorDefaultFloatSimdFU(), MinorDefaultMemFU(),
-        MinorDefaultMiscFU()]
+        MinorDefaultFloatSimdFU(), MinorDefaultPredFU(),
+        MinorDefaultMemFU(), MinorDefaultMiscFU()]
 
 class ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random']
 
diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py
index 1461b405c..55fb82f84 100644
--- a/src/cpu/o3/FUPool.py
+++ b/src/cpu/o3/FUPool.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2017 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -38,4 +50,4 @@ class FUPool(SimObject):
 
 class DefaultFUPool(FUPool):
     FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(),
-               SIMD_Unit(), WritePort(), RdWrPort(), IprPort() ]
+               SIMD_Unit(), PredALU(), WritePort(), RdWrPort(), IprPort() ]
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
index ef114df09..3b02aab79 100644
--- a/src/cpu/o3/FuncUnitConfig.py
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2010 ARM Limited
+# Copyright (c) 2010, 2017 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -86,6 +86,7 @@ class SIMD_Unit(FUDesc):
                OpDesc(opClass='SimdMultAcc'),
                OpDesc(opClass='SimdShift'),
                OpDesc(opClass='SimdShiftAcc'),
+               OpDesc(opClass='SimdDiv'),
                OpDesc(opClass='SimdSqrt'),
                OpDesc(opClass='SimdFloatAdd'),
                OpDesc(opClass='SimdFloatAlu'),
@@ -95,9 +96,18 @@ class SIMD_Unit(FUDesc):
                OpDesc(opClass='SimdFloatMisc'),
                OpDesc(opClass='SimdFloatMult'),
                OpDesc(opClass='SimdFloatMultAcc'),
-               OpDesc(opClass='SimdFloatSqrt') ]
+               OpDesc(opClass='SimdFloatSqrt'),
+               OpDesc(opClass='SimdReduceAdd'),
+               OpDesc(opClass='SimdReduceAlu'),
+               OpDesc(opClass='SimdReduceCmp'),
+               OpDesc(opClass='SimdFloatReduceAdd'),
+               OpDesc(opClass='SimdFloatReduceCmp') ]
     count = 4
 
+class PredALU(FUDesc):
+    opList = [ OpDesc(opClass='SimdPredAlu') ]
+    count = 1
+
 class ReadPort(FUDesc):
     opList = [ OpDesc(opClass='MemRead'),
                OpDesc(opClass='FloatMemRead') ]
diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh
index 1bb88e1cd..ab5bdf247 100644
--- a/src/cpu/op_class.hh
+++ b/src/cpu/op_class.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010,2018 ARM Limited
+ * Copyright (c) 2010, 2017-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -73,7 +73,11 @@ static const OpClass SimdMultOp = Enums::SimdMult;
 static const OpClass SimdMultAccOp = Enums::SimdMultAcc;
 static const OpClass SimdShiftOp = Enums::SimdShift;
 static const OpClass SimdShiftAccOp = Enums::SimdShiftAcc;
+static const OpClass SimdDivOp = Enums::SimdDiv;
 static const OpClass SimdSqrtOp = Enums::SimdSqrt;
+static const OpClass SimdReduceAddOp = Enums::SimdReduceAdd;
+static const OpClass SimdReduceAluOp = Enums::SimdReduceAlu;
+static const OpClass SimdReduceCmpOp = Enums::SimdReduceCmp;
 static const OpClass SimdFloatAddOp = Enums::SimdFloatAdd;
 static const OpClass SimdFloatAluOp = Enums::SimdFloatAlu;
 static const OpClass SimdFloatCmpOp = Enums::SimdFloatCmp;
@@ -83,6 +87,8 @@ static const OpClass SimdFloatMiscOp = Enums::SimdFloatMisc;
 static const OpClass SimdFloatMultOp = Enums::SimdFloatMult;
 static const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc;
 static const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt;
+static const OpClass SimdFloatReduceCmpOp = Enums::SimdFloatReduceCmp;
+static const OpClass SimdFloatReduceAddOp = Enums::SimdFloatReduceAdd;
 static const OpClass SimdAesOp = Enums::SimdAes;
 static const OpClass SimdAesMixOp = Enums::SimdAesMix;
 static const OpClass SimdSha1HashOp = Enums::SimdSha1Hash;
@@ -91,6 +97,7 @@ static const OpClass SimdSha256HashOp = Enums::SimdSha256Hash;
 static const OpClass SimdSha256Hash2Op = Enums::SimdSha256Hash2;
 static const OpClass SimdShaSigma2Op = Enums::SimdShaSigma2;
 static const OpClass SimdShaSigma3Op = Enums::SimdShaSigma3;
+static const OpClass SimdPredAluOp = Enums::SimdPredAlu;
 static const OpClass MemReadOp = Enums::MemRead;
 static const OpClass MemWriteOp = Enums::MemWrite;
 static const OpClass FloatMemReadOp = Enums::FloatMemRead;
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index f86acedd6..c18bac2ef 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2001-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -66,7 +78,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            BaseTLB *_dtb, TheISA::ISA *_isa)
     : ThreadState(_cpu, _thread_num, _process), isa(_isa),
       predicate(false), system(_sys),
-      itb(_itb), dtb(_dtb)
+      itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
 {
     clearArchRegs();
     tc = new ProxyThreadContext<SimpleThread>(this);
@@ -77,7 +89,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            BaseTLB *_itb, BaseTLB *_dtb,
                            TheISA::ISA *_isa, bool use_kernel_stats)
     : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
-      dtb(_dtb)
+      dtb(_dtb), decoder(TheISA::Decoder(_isa))
 {
     tc = new ProxyThreadContext<SimpleThread>(this);