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authorGabe Black <gblack@eecs.umich.edu>2006-11-16 12:34:10 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-16 12:34:10 -0500
commitcd5b33b9ff4016427fa93655f4bbd9030c4f5612 (patch)
treeb449360088378c982f59568c0a2da0c45cb08c59 /src/cpu
parent079dd454175ab7fdb3cc429f3cf199bd243c3776 (diff)
downloadgem5-cd5b33b9ff4016427fa93655f4bbd9030c4f5612.tar.xz
Fixes for SPARC_FS
configs/common/FSConfig.py: Make a SPARC system create an IO bus. src/python/m5/objects/T1000.py: Create a T1000 platform src/arch/sparc/miscregfile.cc: Initialize the strand status register to the value legion provides. src/cpu/exetrace.cc: Truncate an ExtMachInst to a MachInst before comparing with Legion. --HG-- extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/exetrace.cc4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 113f0fe74..a2e6d2d33 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -247,8 +247,10 @@ Trace::InstRecord::dump(ostream &outs)
if (shared_data->flags == OWN_M5) {
if (lgnPc != m5Pc)
diffPC = true;
- if (shared_data->instruction != staticInst->machInst)
+ if (shared_data->instruction !=
+ (SparcISA::MachInst)staticInst->machInst) {
diffInst = true;
+ }
for (int i = 0; i < TheISA::NumRegularIntRegs; i++) {
if (thread->readIntReg(i) != shared_data->intregs[i]) {
diffRegs = true;