sim: separate nextCycle() and clockEdge() in clockedObjects

Previously, nextCycle() could return the *current* cycle if the current tick was
already aligned with the clock edge. This behavior is not only confusing (not
quite what the function name implies), but also caused problems in the
drainResume() function. When exiting/re-entering the sim loop (e.g., to take
checkpoints), the CPUs will drain and resume. Due to the previous behavior of
nextCycle(), the CPU tick events were being rescheduled in the same ticks that
were already processed before draining. This caused divergence from runs that
did not exit/re-entered the sim loop. (Initially a cycle difference, but a
significant impact later on.)

This patch separates out the two behaviors (nextCycle() and clockEdge()),
uses nextCycle() in drainResume, and uses clockEdge() everywhere else.
Nothing (other than name) should change except for the drainResume timing.

3 files changed, 6 insertions, 6 deletions

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 5c07621e3..2c6b49d82 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -1715,7 +1715,7 @@ InOrderCPU::wakeCPU()
 
     numCycles += extra_cycles;
 
-    schedule(&tickEvent, nextCycle());
+    schedule(&tickEvent, clockEdge());
 }
 
 // Lots of copied full system code...place into BaseCPU class?
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 9caa49ad6..99beaa176 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1720,7 +1720,7 @@ FullO3CPU<Impl>::wakeCPU()
     idleCycles += cycles;
     numCycles += cycles;
 
-    schedule(tickEvent, nextCycle());
+    schedule(tickEvent, clockEdge());
 }
 
 template <class Impl>
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ab4ea9256..1f453ca63 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -120,7 +120,7 @@ TimingSimpleCPU::drain(DrainManager *drain_manager)
         // succeed on the first attempt. We need to reschedule it if
         // the CPU is waiting for a microcode routine to complete.
         if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled())
-            schedule(fetchEvent, nextCycle());
+            schedule(fetchEvent, clockEdge());
 
         return 1;
     }
@@ -616,7 +616,7 @@ TimingSimpleCPU::advanceInst(Fault fault)
     if (fault != NoFault) {
         advancePC(fault);
         DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
-        reschedule(fetchEvent, nextCycle(), true);
+        reschedule(fetchEvent, clockEdge(), true);
         _status = Faulting;
         return;
     }
@@ -715,7 +715,7 @@ TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
 {
     DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
     // delay processing of returned data until next CPU clock edge
-    Tick next_tick = cpu->nextCycle();
+    Tick next_tick = cpu->clockEdge();
 
     if (next_tick == curTick())
         cpu->completeIfetch(pkt);
@@ -807,7 +807,7 @@ bool
 TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
 {
     // delay processing of returned data until next CPU clock edge
-    Tick next_tick = cpu->nextCycle();
+    Tick next_tick = cpu->clockEdge();
 
     if (next_tick == curTick()) {
         cpu->completeDataAccess(pkt);