python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

27 files changed, 80 insertions, 71 deletions

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index e02d36724..007c869af 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -52,51 +52,51 @@ from m5.params import *
 from m5.proxy import *
 from m5.util.fdthelper import *
 
-from XBar import L2XBar
-from InstTracer import InstTracer
-from CPUTracers import ExeTracer
-from MemObject import MemObject
-from SubSystem import SubSystem
-from ClockDomain import *
-from Platform import Platform
+from m5.objects.XBar import L2XBar
+from m5.objects.InstTracer import InstTracer
+from m5.objects.CPUTracers import ExeTracer
+from m5.objects.MemObject import MemObject
+from m5.objects.SubSystem import SubSystem
+from m5.objects.ClockDomain import *
+from m5.objects.Platform import Platform
 
 default_tracer = ExeTracer()
 
 if buildEnv['TARGET_ISA'] == 'alpha':
-    from AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
-    from AlphaInterrupts import AlphaInterrupts
-    from AlphaISA import AlphaISA
+    from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
+    from m5.objects.AlphaInterrupts import AlphaInterrupts
+    from m5.objects.AlphaISA import AlphaISA
     default_isa_class = AlphaISA
 elif buildEnv['TARGET_ISA'] == 'sparc':
-    from SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
-    from SparcInterrupts import SparcInterrupts
-    from SparcISA import SparcISA
+    from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
+    from m5.objects.SparcInterrupts import SparcInterrupts
+    from m5.objects.SparcISA import SparcISA
     default_isa_class = SparcISA
 elif buildEnv['TARGET_ISA'] == 'x86':
-    from X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
-    from X86LocalApic import X86LocalApic
-    from X86ISA import X86ISA
+    from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
+    from m5.objects.X86LocalApic import X86LocalApic
+    from m5.objects.X86ISA import X86ISA
     default_isa_class = X86ISA
 elif buildEnv['TARGET_ISA'] == 'mips':
-    from MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
-    from MipsInterrupts import MipsInterrupts
-    from MipsISA import MipsISA
+    from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
+    from m5.objects.MipsInterrupts import MipsInterrupts
+    from m5.objects.MipsISA import MipsISA
     default_isa_class = MipsISA
 elif buildEnv['TARGET_ISA'] == 'arm':
-    from ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
-    from ArmTLB import ArmStage2IMMU, ArmStage2DMMU
-    from ArmInterrupts import ArmInterrupts
-    from ArmISA import ArmISA
+    from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
+    from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU
+    from m5.objects.ArmInterrupts import ArmInterrupts
+    from m5.objects.ArmISA import ArmISA
     default_isa_class = ArmISA
 elif buildEnv['TARGET_ISA'] == 'power':
-    from PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
-    from PowerInterrupts import PowerInterrupts
-    from PowerISA import PowerISA
+    from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
+    from m5.objects.PowerInterrupts import PowerInterrupts
+    from m5.objects.PowerISA import PowerISA
     default_isa_class = PowerISA
 elif buildEnv['TARGET_ISA'] == 'riscv':
-    from RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
-    from RiscvInterrupts import RiscvInterrupts
-    from RiscvISA import RiscvISA
+    from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
+    from m5.objects.RiscvInterrupts import RiscvInterrupts
+    from m5.objects.RiscvISA import RiscvISA
     default_isa_class = RiscvISA
 
 class BaseCPU(MemObject):
diff --git a/src/cpu/CPUTracers.py b/src/cpu/CPUTracers.py
index df7a8939f..16d003683 100644
--- a/src/cpu/CPUTracers.py
+++ b/src/cpu/CPUTracers.py
@@ -28,7 +28,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from InstTracer import InstTracer
+from m5.objects.InstTracer import InstTracer
 
 class ExeTracer(InstTracer):
     type = 'ExeTracer'
diff --git a/src/cpu/CheckerCPU.py b/src/cpu/CheckerCPU.py
index f08b59f20..51c1e5c3c 100644
--- a/src/cpu/CheckerCPU.py
+++ b/src/cpu/CheckerCPU.py
@@ -27,7 +27,8 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from BaseCPU import BaseCPU
+
+from m5.objects.BaseCPU import BaseCPU
 
 class CheckerCPU(BaseCPU):
     type = 'CheckerCPU'
diff --git a/src/cpu/DummyChecker.py b/src/cpu/DummyChecker.py
index 3bf021a14..300909209 100644
--- a/src/cpu/DummyChecker.py
+++ b/src/cpu/DummyChecker.py
@@ -36,7 +36,7 @@
 # Authors: Geoffrey Blake
 
 from m5.params import *
-from CheckerCPU import CheckerCPU
+from m5.objects.CheckerCPU import CheckerCPU
 
 class DummyChecker(CheckerCPU):
     type = 'DummyChecker'
diff --git a/src/cpu/InstPBTrace.py b/src/cpu/InstPBTrace.py
index 2576fc944..8feedd60c 100644
--- a/src/cpu/InstPBTrace.py
+++ b/src/cpu/InstPBTrace.py
@@ -28,7 +28,8 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from InstTracer import InstTracer
+
+from m5.objects.InstTracer import InstTracer
 
 class InstPBTrace(InstTracer):
     type = 'InstPBTrace'
diff --git a/src/cpu/kvm/BaseKvmCPU.py b/src/cpu/kvm/BaseKvmCPU.py
index cb9bf481a..c9e64bd69 100644
--- a/src/cpu/kvm/BaseKvmCPU.py
+++ b/src/cpu/kvm/BaseKvmCPU.py
@@ -39,8 +39,8 @@ from m5.SimObject import *
 from m5.params import *
 from m5.proxy import *
 
-from BaseCPU import BaseCPU
-from KvmVM import KvmVM
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.KvmVM import KvmVM
 
 class BaseKvmCPU(BaseCPU):
     type = 'BaseKvmCPU'
diff --git a/src/cpu/kvm/X86KvmCPU.py b/src/cpu/kvm/X86KvmCPU.py
index 411db7dbe..a632bff3f 100644
--- a/src/cpu/kvm/X86KvmCPU.py
+++ b/src/cpu/kvm/X86KvmCPU.py
@@ -28,7 +28,8 @@
 
 from m5.params import *
 from m5.SimObject import *
-from BaseKvmCPU import BaseKvmCPU
+
+from m5.objects.BaseKvmCPU import BaseKvmCPU
 
 class X86KvmCPU(BaseKvmCPU):
     type = 'X86KvmCPU'
diff --git a/src/cpu/minor/MinorCPU.py b/src/cpu/minor/MinorCPU.py
index 9e285a4d1..bb4df82f0 100644
--- a/src/cpu/minor/MinorCPU.py
+++ b/src/cpu/minor/MinorCPU.py
@@ -46,12 +46,12 @@ from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
-from BaseCPU import BaseCPU
-from DummyChecker import DummyChecker
-from BranchPredictor import *
-from TimingExpr import TimingExpr
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.DummyChecker import DummyChecker
+from m5.objects.BranchPredictor import *
+from m5.objects.TimingExpr import TimingExpr
 
-from FuncUnit import OpClass
+from m5.objects.FuncUnit import OpClass
 
 class MinorOpClass(SimObject):
     """Boxing of OpClass to get around build problems and provide a hook for
diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py
index 0f4ea67c7..1461b405c 100644
--- a/src/cpu/o3/FUPool.py
+++ b/src/cpu/o3/FUPool.py
@@ -28,8 +28,8 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from FuncUnit import *
-from FuncUnitConfig import *
+from m5.objects.FuncUnit import *
+from m5.objects.FuncUnitConfig import *
 
 class FUPool(SimObject):
     type = 'FUPool'
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
index f0c70f55a..ef114df09 100644
--- a/src/cpu/o3/FuncUnitConfig.py
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -41,7 +41,8 @@
 from m5.SimObject import SimObject
 from m5.defines import buildEnv
 from m5.params import *
-from FuncUnit import *
+
+from m5.objects.FuncUnit import *
 
 class IntALU(FUDesc):
     opList = [ OpDesc(opClass='IntAlu') ]
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index e73c09334..8e17d9a3f 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -43,10 +43,11 @@ from __future__ import print_function
 from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
-from BaseCPU import BaseCPU
-from FUPool import *
-from O3Checker import O3Checker
-from BranchPredictor import *
+
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.FUPool import *
+from m5.objects.O3Checker import O3Checker
+from m5.objects.BranchPredictor import *
 
 class FetchPolicy(ScopedEnum):
     vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ]
@@ -178,7 +179,7 @@ class DerivO3CPU(BaseCPU):
 
     def addCheckerCpu(self):
         if buildEnv['TARGET_ISA'] in ['arm']:
-            from ArmTLB import ArmTLB
+            from m5.objects.ArmTLB import ArmTLB
 
             self.checker = O3Checker(workload=self.workload,
                                      exitOnError=False,
diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py
index f21a038c4..20d59c1f4 100644
--- a/src/cpu/o3/O3Checker.py
+++ b/src/cpu/o3/O3Checker.py
@@ -27,7 +27,7 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from CheckerCPU import CheckerCPU
+from m5.objects.CheckerCPU import CheckerCPU
 
 class O3Checker(CheckerCPU):
     type = 'O3Checker'
diff --git a/src/cpu/o3/probe/ElasticTrace.py b/src/cpu/o3/probe/ElasticTrace.py
index 20057ab97..d60681d3f 100644
--- a/src/cpu/o3/probe/ElasticTrace.py
+++ b/src/cpu/o3/probe/ElasticTrace.py
@@ -37,7 +37,7 @@
 #          Andreas Hansson
 #          Thomas Grass
 
-from Probe import *
+from m5.objects.Probe import *
 
 class ElasticTrace(ProbeListenerObject):
     type = 'ElasticTrace'
diff --git a/src/cpu/o3/probe/SimpleTrace.py b/src/cpu/o3/probe/SimpleTrace.py
index eeec58ef0..9572aa218 100644
--- a/src/cpu/o3/probe/SimpleTrace.py
+++ b/src/cpu/o3/probe/SimpleTrace.py
@@ -35,7 +35,7 @@
 #
 # Authors: Matt Horsnell
 
-from Probe import *
+from m5.objects.Probe import *
 
 class SimpleTrace(ProbeListenerObject):
     type = 'SimpleTrace'
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 15a3feb69..d9dee461b 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -39,8 +39,8 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from BaseSimpleCPU import BaseSimpleCPU
-from SimPoint import SimPoint
+from m5.objects.BaseSimpleCPU import BaseSimpleCPU
+from m5.objects.SimPoint import SimPoint
 
 class AtomicSimpleCPU(BaseSimpleCPU):
     """Simple CPU model executing a configurable number of
diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py
index b40458482..6714295d2 100644
--- a/src/cpu/simple/BaseSimpleCPU.py
+++ b/src/cpu/simple/BaseSimpleCPU.py
@@ -30,9 +30,10 @@ from __future__ import print_function
 
 from m5.defines import buildEnv
 from m5.params import *
-from BaseCPU import BaseCPU
-from DummyChecker import DummyChecker
-from BranchPredictor import *
+
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.DummyChecker import DummyChecker
+from m5.objects.BranchPredictor import *
 
 class BaseSimpleCPU(BaseCPU):
     type = 'BaseSimpleCPU'
@@ -41,7 +42,7 @@ class BaseSimpleCPU(BaseCPU):
 
     def addCheckerCpu(self):
         if buildEnv['TARGET_ISA'] in ['arm']:
-            from ArmTLB import ArmTLB
+            from m5.objects.ArmTLB import ArmTLB
 
             self.checker = DummyChecker(workload = self.workload)
             self.checker.itb = ArmTLB(size = self.itb.size)
diff --git a/src/cpu/simple/NonCachingSimpleCPU.py b/src/cpu/simple/NonCachingSimpleCPU.py
index 2905a79ac..3fe0e02c3 100644
--- a/src/cpu/simple/NonCachingSimpleCPU.py
+++ b/src/cpu/simple/NonCachingSimpleCPU.py
@@ -36,7 +36,7 @@
 # Authors: Andreas Sandberg
 
 from m5.params import *
-from AtomicSimpleCPU import AtomicSimpleCPU
+from m5.objects.AtomicSimpleCPU import AtomicSimpleCPU
 
 class NonCachingSimpleCPU(AtomicSimpleCPU):
     """Simple CPU model based on the atomic CPU. Unlike the atomic CPU,
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index 25149eaa8..134c8bb35 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -27,7 +27,8 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from BaseSimpleCPU import BaseSimpleCPU
+
+from m5.objects.BaseSimpleCPU import BaseSimpleCPU
 
 class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'
diff --git a/src/cpu/simple/probes/SimPoint.py b/src/cpu/simple/probes/SimPoint.py
index ac6ec0730..14766a791 100644
--- a/src/cpu/simple/probes/SimPoint.py
+++ b/src/cpu/simple/probes/SimPoint.py
@@ -36,7 +36,7 @@
 # Authors: Curtis Dunham
 
 from m5.params import *
-from Probe import ProbeListenerObject
+from m5.objects.Probe import ProbeListenerObject
 
 class SimPoint(ProbeListenerObject):
     """Probe for collecting SimPoint Basic Block Vectors (BBVs)."""
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py
index df1205659..9f90c9b41 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.py
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.py
@@ -27,10 +27,11 @@
 # Authors: Brad Beckmann
 
 from m5.SimObject import SimObject
-from MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
 
+from m5.objects.MemObject import MemObject
+
 class DirectedGenerator(SimObject):
     type = 'DirectedGenerator'
     abstract = True
diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
index 261e643c1..4c7772348 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
@@ -26,7 +26,7 @@
 #
 # Authors: Tushar Krishna
 
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
 
diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py
index d09537639..5585b1f70 100644
--- a/src/cpu/testers/memtest/MemTest.py
+++ b/src/cpu/testers/memtest/MemTest.py
@@ -38,11 +38,11 @@
 #
 # Authors: Nathan Binkert
 #          Andreas Hansson
-
-from MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
 
+from m5.objects.MemObject import MemObject
+
 class MemTest(MemObject):
     type = 'MemTest'
     cxx_header = "cpu/testers/memtest/memtest.hh"
diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py
index f12485566..2ac1697fd 100644
--- a/src/cpu/testers/rubytest/RubyTester.py
+++ b/src/cpu/testers/rubytest/RubyTester.py
@@ -25,11 +25,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-
-from MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
 
+from m5.objects.MemObject import MemObject
+
 class RubyTester(MemObject):
     type = 'RubyTester'
     cxx_header = "cpu/testers/rubytest/RubyTester.hh"
diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
index dbe0c848b..94e3319d5 100644
--- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
@@ -39,7 +39,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 # Types of Stream Generators.
 # Those are orthogonal to the other generators in the TrafficGen
diff --git a/src/cpu/testers/traffic_gen/PyTrafficGen.py b/src/cpu/testers/traffic_gen/PyTrafficGen.py
index c29ad0a3b..c8829ecc8 100644
--- a/src/cpu/testers/traffic_gen/PyTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/PyTrafficGen.py
@@ -37,7 +37,8 @@
 
 from m5.defines import buildEnv
 from m5.SimObject import *
-from BaseTrafficGen import *
+
+from m5.objects.BaseTrafficGen import *
 
 class PyTrafficGen(BaseTrafficGen):
     type = 'PyTrafficGen'
diff --git a/src/cpu/testers/traffic_gen/TrafficGen.py b/src/cpu/testers/traffic_gen/TrafficGen.py
index f1e094821..af6c4902c 100644
--- a/src/cpu/testers/traffic_gen/TrafficGen.py
+++ b/src/cpu/testers/traffic_gen/TrafficGen.py
@@ -38,7 +38,7 @@
 #          Sascha Bischoff
 
 from m5.params import *
-from BaseTrafficGen import *
+from m5.objects.BaseTrafficGen import *
 
 # The behaviour of this traffic generator is specified in a
 # configuration file, and this file describes a state transition graph
diff --git a/src/cpu/trace/TraceCPU.py b/src/cpu/trace/TraceCPU.py
index e108b1a50..0838dd8c4 100644
--- a/src/cpu/trace/TraceCPU.py
+++ b/src/cpu/trace/TraceCPU.py
@@ -38,7 +38,7 @@
 #          Thomas Grass
 
 from m5.params import *
-from BaseCPU import BaseCPU
+from m5.objects.BaseCPU import BaseCPU
 
 class TraceCPU(BaseCPU):
     """Trace CPU model which replays traces generated in a prior simulation