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authorAndreas Sandberg <andreas.sandberg@arm.com>2015-12-10 10:35:18 +0000
committerAndreas Sandberg <andreas.sandberg@arm.com>2015-12-10 10:35:18 +0000
commit23c961a0fd97251ee7c760bc2ff2a011a417ad9b (patch)
tree0481b7552303373cd3722156b1cef92d813de215 /src/dev/Ethernet.py
parentef097ac4381ad2f14acda640ae198f04d9f7988d (diff)
downloadgem5-23c961a0fd97251ee7c760bc2ff2a011a417ad9b.tar.xz
dev: Move network devices to src/dev/net/
--HG-- rename : src/dev/Ethernet.py => src/dev/net/Ethernet.py rename : src/dev/etherbus.cc => src/dev/net/etherbus.cc rename : src/dev/etherbus.hh => src/dev/net/etherbus.hh rename : src/dev/etherdevice.cc => src/dev/net/etherdevice.cc rename : src/dev/etherdevice.hh => src/dev/net/etherdevice.hh rename : src/dev/etherdump.cc => src/dev/net/etherdump.cc rename : src/dev/etherdump.hh => src/dev/net/etherdump.hh rename : src/dev/etherint.cc => src/dev/net/etherint.cc rename : src/dev/etherint.hh => src/dev/net/etherint.hh rename : src/dev/etherlink.cc => src/dev/net/etherlink.cc rename : src/dev/etherlink.hh => src/dev/net/etherlink.hh rename : src/dev/etherobject.hh => src/dev/net/etherobject.hh rename : src/dev/etherpkt.cc => src/dev/net/etherpkt.cc rename : src/dev/etherpkt.hh => src/dev/net/etherpkt.hh rename : src/dev/ethertap.cc => src/dev/net/ethertap.cc rename : src/dev/ethertap.hh => src/dev/net/ethertap.hh rename : src/dev/i8254xGBe.cc => src/dev/net/i8254xGBe.cc rename : src/dev/i8254xGBe.hh => src/dev/net/i8254xGBe.hh rename : src/dev/i8254xGBe_defs.hh => src/dev/net/i8254xGBe_defs.hh rename : src/dev/multi_etherlink.cc => src/dev/net/multi_etherlink.cc rename : src/dev/multi_etherlink.hh => src/dev/net/multi_etherlink.hh rename : src/dev/multi_iface.cc => src/dev/net/multi_iface.cc rename : src/dev/multi_iface.hh => src/dev/net/multi_iface.hh rename : src/dev/multi_packet.cc => src/dev/net/multi_packet.cc rename : src/dev/multi_packet.hh => src/dev/net/multi_packet.hh rename : src/dev/ns_gige.cc => src/dev/net/ns_gige.cc rename : src/dev/ns_gige.hh => src/dev/net/ns_gige.hh rename : src/dev/ns_gige_reg.h => src/dev/net/ns_gige_reg.h rename : src/dev/pktfifo.cc => src/dev/net/pktfifo.cc rename : src/dev/pktfifo.hh => src/dev/net/pktfifo.hh rename : src/dev/sinic.cc => src/dev/net/sinic.cc rename : src/dev/sinic.hh => src/dev/net/sinic.hh rename : src/dev/sinicreg.hh => src/dev/net/sinicreg.hh rename : src/dev/tcp_iface.cc => src/dev/net/tcp_iface.cc rename : src/dev/tcp_iface.hh => src/dev/net/tcp_iface.hh
Diffstat (limited to 'src/dev/Ethernet.py')
-rw-r--r--src/dev/Ethernet.py245
1 files changed, 0 insertions, 245 deletions
diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py
deleted file mode 100644
index 89d1bad89..000000000
--- a/src/dev/Ethernet.py
+++ /dev/null
@@ -1,245 +0,0 @@
-# Copyright (c) 2015 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder. You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Copyright (c) 2005-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert
-
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-from PciDevice import PciDevice
-
-class EtherObject(SimObject):
- type = 'EtherObject'
- abstract = True
- cxx_header = "dev/etherobject.hh"
-
-class EtherLink(EtherObject):
- type = 'EtherLink'
- cxx_header = "dev/etherlink.hh"
- int0 = SlavePort("interface 0")
- int1 = SlavePort("interface 1")
- delay = Param.Latency('0us', "packet transmit delay")
- delay_var = Param.Latency('0ns', "packet transmit delay variability")
- speed = Param.NetworkBandwidth('1Gbps', "link speed")
- dump = Param.EtherDump(NULL, "dump object")
-
-class MultiEtherLink(EtherObject):
- type = 'MultiEtherLink'
- cxx_header = "dev/multi_etherlink.hh"
- int0 = SlavePort("interface 0")
- delay = Param.Latency('0us', "packet transmit delay")
- delay_var = Param.Latency('0ns', "packet transmit delay variability")
- speed = Param.NetworkBandwidth('1Gbps', "link speed")
- dump = Param.EtherDump(NULL, "dump object")
- multi_rank = Param.UInt32('0', "Rank of the this gem5 process (multi run)")
- sync_start = Param.Latency('5200000000000t', "first multi sync barrier")
- sync_repeat = Param.Latency('10us', "multi sync barrier repeat")
- server_name = Param.String('localhost', "Message server name")
- server_port = Param.UInt32('2200', "Message server port")
-
-class EtherBus(EtherObject):
- type = 'EtherBus'
- cxx_header = "dev/etherbus.hh"
- loopback = Param.Bool(True, "send packet back to the sending interface")
- dump = Param.EtherDump(NULL, "dump object")
- speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
-
-class EtherTap(EtherObject):
- type = 'EtherTap'
- cxx_header = "dev/ethertap.hh"
- bufsz = Param.Int(10000, "tap buffer size")
- dump = Param.EtherDump(NULL, "dump object")
- port = Param.UInt16(3500, "tap port")
-
-class EtherDump(SimObject):
- type = 'EtherDump'
- cxx_header = "dev/etherdump.hh"
- file = Param.String("dump file")
- maxlen = Param.Int(96, "max portion of packet data to dump")
-
-class EtherDevice(PciDevice):
- type = 'EtherDevice'
- abstract = True
- cxx_header = "dev/etherdevice.hh"
- interface = MasterPort("Ethernet Interface")
-
-class IGbE(EtherDevice):
- # Base class for two IGbE adapters listed above
- type = 'IGbE'
- cxx_header = "dev/i8254xGBe.hh"
- hardware_address = Param.EthernetAddr(NextEthernetAddr,
- "Ethernet Hardware Address")
- rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
- tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
- rx_desc_cache_size = Param.Int(64,
- "Number of enteries in the rx descriptor cache")
- tx_desc_cache_size = Param.Int(64,
- "Number of enteries in the rx descriptor cache")
- VendorID = 0x8086
- SubsystemID = 0x1008
- SubsystemVendorID = 0x8086
- Status = 0x0000
- SubClassCode = 0x00
- ClassCode = 0x02
- ProgIF = 0x00
- BAR0 = 0x00000000
- BAR1 = 0x00000000
- BAR2 = 0x00000000
- BAR3 = 0x00000000
- BAR4 = 0x00000000
- BAR5 = 0x00000000
- MaximumLatency = 0x00
- MinimumGrant = 0xff
- InterruptLine = 0x1e
- InterruptPin = 0x01
- BAR0Size = '128kB'
- wb_delay = Param.Latency('10ns', "delay before desc writeback occurs")
- fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs")
- fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs")
- wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs")
- tx_read_delay = Param.Latency('0ns', "delay after tx dma read")
- rx_write_delay = Param.Latency('0ns', "delay after rx dma read")
- phy_pid = Param.UInt16("Phy PID that corresponds to device ID")
- phy_epid = Param.UInt16("Phy EPID that corresponds to device ID")
-
-class IGbE_e1000(IGbE):
- # Older Intel 8254x based gigabit ethernet adapter
- # Uses Intel e1000 driver
- DeviceID = 0x1075
- phy_pid = 0x02A8
- phy_epid = 0x0380
-
-class IGbE_igb(IGbE):
- # Newer Intel 8257x based gigabit ethernet adapter
- # Uses Intel igb driver and in theory supports packet splitting and LRO
- DeviceID = 0x10C9
- phy_pid = 0x0141
- phy_epid = 0x0CC0
-
-class EtherDevBase(EtherDevice):
- type = 'EtherDevBase'
- abstract = True
- cxx_header = "dev/etherdevice.hh"
-
- hardware_address = Param.EthernetAddr(NextEthernetAddr,
- "Ethernet Hardware Address")
-
- dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
- dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
- dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
- dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
-
- rx_delay = Param.Latency('1us', "Receive Delay")
- tx_delay = Param.Latency('1us', "Transmit Delay")
- rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
- tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
-
- rx_filter = Param.Bool(True, "Enable Receive Filter")
- intr_delay = Param.Latency('10us', "Interrupt propagation delay")
- rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
- tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
- rss = Param.Bool(False, "Receive Side Scaling")
-
-class NSGigE(EtherDevBase):
- type = 'NSGigE'
- cxx_header = "dev/ns_gige.hh"
-
- dma_data_free = Param.Bool(False, "DMA of Data is free")
- dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
- dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
-
- VendorID = 0x100B
- DeviceID = 0x0022
- Status = 0x0290
- SubClassCode = 0x00
- ClassCode = 0x02
- ProgIF = 0x00
- BAR0 = 0x00000001
- BAR1 = 0x00000000
- BAR2 = 0x00000000
- BAR3 = 0x00000000
- BAR4 = 0x00000000
- BAR5 = 0x00000000
- MaximumLatency = 0x34
- MinimumGrant = 0xb0
- InterruptLine = 0x1e
- InterruptPin = 0x01
- BAR0Size = '256B'
- BAR1Size = '4kB'
-
-
-
-class Sinic(EtherDevBase):
- type = 'Sinic'
- cxx_class = 'Sinic::Device'
- cxx_header = "dev/sinic.hh"
-
- rx_max_copy = Param.MemorySize('1514B', "rx max copy")
- tx_max_copy = Param.MemorySize('16kB', "tx max copy")
- rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
- rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
- rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
- tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
- tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
- virtual_count = Param.UInt32(1, "Virtualized SINIC")
- zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold")
- zero_copy_threshold = Param.UInt32(256,
- "Only zero copy above this threshold")
- zero_copy = Param.Bool(False, "Zero copy receive")
- delay_copy = Param.Bool(False, "Delayed copy transmit")
- virtual_addr = Param.Bool(False, "Virtual addressing")
-
- VendorID = 0x1291
- DeviceID = 0x1293
- Status = 0x0290
- SubClassCode = 0x00
- ClassCode = 0x02
- ProgIF = 0x00
- BAR0 = 0x00000000
- BAR1 = 0x00000000
- BAR2 = 0x00000000
- BAR3 = 0x00000000
- BAR4 = 0x00000000
- BAR5 = 0x00000000
- MaximumLatency = 0x34
- MinimumGrant = 0xb0
- InterruptLine = 0x1e
- InterruptPin = 0x01
- BAR0Size = '64kB'
-
-