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authorAndreas Sandberg <Andreas.Sandberg@arm.com>2012-11-02 11:32:01 -0500
committerAndreas Sandberg <Andreas.Sandberg@arm.com>2012-11-02 11:32:01 -0500
commitc0ab52799ca4ebd0a51363cfedd0658e6d79b842 (patch)
treeafdf65e4593c64bbc1d5b511aacbaf0fa4b558ad /src/dev/Ethernet.py
parent044a6525876efc61838dffa89ac52425d510b754 (diff)
downloadgem5-c0ab52799ca4ebd0a51363cfedd0658e6d79b842.tar.xz
sim: Include object header files in SWIG interfaces
When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it.
Diffstat (limited to 'src/dev/Ethernet.py')
-rw-r--r--src/dev/Ethernet.py9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py
index 1afbce8ee..57d867fbe 100644
--- a/src/dev/Ethernet.py
+++ b/src/dev/Ethernet.py
@@ -34,9 +34,11 @@ from Pci import PciDevice
class EtherObject(SimObject):
type = 'EtherObject'
abstract = True
+ cxx_header = "dev/etherobject.hh"
class EtherLink(EtherObject):
type = 'EtherLink'
+ cxx_header = "dev/etherlink.hh"
int0 = SlavePort("interface 0")
int1 = SlavePort("interface 1")
delay = Param.Latency('0us', "packet transmit delay")
@@ -46,29 +48,34 @@ class EtherLink(EtherObject):
class EtherBus(EtherObject):
type = 'EtherBus'
+ cxx_header = "dev/etherbus.hh"
loopback = Param.Bool(True, "send packet back to the sending interface")
dump = Param.EtherDump(NULL, "dump object")
speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
class EtherTap(EtherObject):
type = 'EtherTap'
+ cxx_header = "dev/ethertap.hh"
bufsz = Param.Int(10000, "tap buffer size")
dump = Param.EtherDump(NULL, "dump object")
port = Param.UInt16(3500, "tap port")
class EtherDump(SimObject):
type = 'EtherDump'
+ cxx_header = "dev/etherdump.hh"
file = Param.String("dump file")
maxlen = Param.Int(96, "max portion of packet data to dump")
class EtherDevice(PciDevice):
type = 'EtherDevice'
abstract = True
+ cxx_header = "dev/etherdevice.hh"
interface = MasterPort("Ethernet Interface")
class IGbE(EtherDevice):
# Base class for two IGbE adapters listed above
type = 'IGbE'
+ cxx_header = "dev/i8254xGBe.hh"
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
use_flow_control = Param.Bool(False,
@@ -149,6 +156,7 @@ class EtherDevBase(EtherDevice):
class NSGigE(EtherDevBase):
type = 'NSGigE'
+ cxx_header = "dev/ns_gige.hh"
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
@@ -178,6 +186,7 @@ class NSGigE(EtherDevBase):
class Sinic(EtherDevBase):
type = 'Sinic'
cxx_class = 'Sinic::Device'
+ cxx_header = "dev/sinic.hh"
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
tx_max_copy = Param.MemorySize('16kB', "tx max copy")