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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-01 00:02:21 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-01 00:02:21 -0800 |
| commit | 3ecc38cb8b882169fb64bf939f709326915f375e (patch) | |
| tree | 08f8a5952311d17f15445f9e24b9f9c57fb054a3 /src/dev/Pci.py | |
| parent | bb7ad80bbe565800b09c38bdc02c12f827ec9240 (diff) | |
| download | gem5-3ecc38cb8b882169fb64bf939f709326915f375e.tar.xz | |
Devices: Add support for legacy fixed IO locations in BARs.
Diffstat (limited to 'src/dev/Pci.py')
| -rw-r--r-- | src/dev/Pci.py | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/dev/Pci.py b/src/dev/Pci.py index b50e1b15c..bd67d82fb 100644 --- a/src/dev/Pci.py +++ b/src/dev/Pci.py @@ -73,6 +73,12 @@ class PciDevice(DmaDevice): BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size") BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size") BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size") + BAR0LegacyIO = Param.Bool(False, "Whether BAR0 is hardwired legacy IO") + BAR1LegacyIO = Param.Bool(False, "Whether BAR1 is hardwired legacy IO") + BAR2LegacyIO = Param.Bool(False, "Whether BAR2 is hardwired legacy IO") + BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO") + BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO") + BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO") CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") SubsystemID = Param.UInt16(0x00, "Subsystem ID") |