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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
| commit | d080581db1f9ee4e1e6d07d2b01c13c67908a391 (patch) | |
| tree | cc484b289fa5a30c4631f9faa1d8b456bffeebfc /src/dev/Pci.py | |
| parent | 7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9 (diff) | |
| parent | 639cb0a42d953ee32bc7e96b0cdfa96cd40e9fc1 (diff) | |
| download | gem5-d080581db1f9ee4e1e6d07d2b01c13c67908a391.tar.xz | |
Merge ARM into the head. ARM will compile but may not actually work.
Diffstat (limited to 'src/dev/Pci.py')
| -rw-r--r-- | src/dev/Pci.py | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/dev/Pci.py b/src/dev/Pci.py index b50e1b15c..bd67d82fb 100644 --- a/src/dev/Pci.py +++ b/src/dev/Pci.py @@ -73,6 +73,12 @@ class PciDevice(DmaDevice): BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size") BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size") BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size") + BAR0LegacyIO = Param.Bool(False, "Whether BAR0 is hardwired legacy IO") + BAR1LegacyIO = Param.Bool(False, "Whether BAR1 is hardwired legacy IO") + BAR2LegacyIO = Param.Bool(False, "Whether BAR2 is hardwired legacy IO") + BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO") + BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO") + BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO") CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") SubsystemID = Param.UInt16(0x00, "Subsystem ID") |