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authorGabe Black <gblack@eecs.umich.edu>2009-04-06 10:19:36 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-04-06 10:19:36 -0700
commitd080581db1f9ee4e1e6d07d2b01c13c67908a391 (patch)
treecc484b289fa5a30c4631f9faa1d8b456bffeebfc /src/dev/alpha/Tsunami.py
parent7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9 (diff)
parent639cb0a42d953ee32bc7e96b0cdfa96cd40e9fc1 (diff)
downloadgem5-d080581db1f9ee4e1e6d07d2b01c13c67908a391.tar.xz
Merge ARM into the head. ARM will compile but may not actually work.
Diffstat (limited to 'src/dev/alpha/Tsunami.py')
-rw-r--r--src/dev/alpha/Tsunami.py10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/dev/alpha/Tsunami.py b/src/dev/alpha/Tsunami.py
index 484976c09..5440486b6 100644
--- a/src/dev/alpha/Tsunami.py
+++ b/src/dev/alpha/Tsunami.py
@@ -28,12 +28,12 @@
from m5.params import *
from m5.proxy import *
+from BadDevice import BadDevice
+from AlphaBackdoor import AlphaBackdoor
from Device import BasicPioDevice, IsaFake, BadAddr
+from Pci import PciConfigAll
from Platform import Platform
-from AlphaConsole import AlphaConsole
from Uart import Uart8250
-from Pci import PciConfigAll
-from BadDevice import BadDevice
class TsunamiCChip(BasicPioDevice):
type = 'TsunamiCChip'
@@ -87,7 +87,7 @@ class Tsunami(Platform):
fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
io = TsunamiIO(pio_addr=0x801fc000000)
uart = Uart8250(pio_addr=0x801fc0003f8)
- console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
+ backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk)
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
@@ -120,4 +120,4 @@ class Tsunami(Platform):
self.fb.pio = bus.port
self.io.pio = bus.port
self.uart.pio = bus.port
- self.console.pio = bus.port
+ self.backdoor.pio = bus.port