Implement Niagara I/O interface and rework interrupts

configs/common/FSConfig.py:
    Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
    get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
    Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Add InterruptVector type
src/arch/sparc/interrupts.hh:
    rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
    Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
    add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
    Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
    InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
    Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
    Add checkSoftInt to check if a softint needs to be posted
    Check that a tickCompare isn't scheduled before scheduling one
    Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
    Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
    get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
    Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
    add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
    update config.ini/out for intrcntrl not having a cpu pointer anymore

--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd

1 files changed, 6 insertions, 6 deletions

diff --git a/src/dev/alpha/tsunami_cchip.cc b/src/dev/alpha/tsunami_cchip.cc
index 15c47984b..118160adf 100644
--- a/src/dev/alpha/tsunami_cchip.cc
+++ b/src/dev/alpha/tsunami_cchip.cc
@@ -372,7 +372,7 @@ TsunamiCChip::write(PacketPtr pkt)
 void
 TsunamiCChip::clearIPI(uint64_t ipintr)
 {
-    int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
+    int numcpus = sys->threadContexts.size();
     assert(numcpus <= Tsunami::Max_CPUs);
 
     if (ipintr) {
@@ -398,7 +398,7 @@ TsunamiCChip::clearIPI(uint64_t ipintr)
 void
 TsunamiCChip::clearITI(uint64_t itintr)
 {
-    int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
+    int numcpus = sys->threadContexts.size();
     assert(numcpus <= Tsunami::Max_CPUs);
 
     if (itintr) {
@@ -418,7 +418,7 @@ TsunamiCChip::clearITI(uint64_t itintr)
 void
 TsunamiCChip::reqIPI(uint64_t ipreq)
 {
-    int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
+    int numcpus = sys->threadContexts.size();
     assert(numcpus <= Tsunami::Max_CPUs);
 
     if (ipreq) {
@@ -445,7 +445,7 @@ TsunamiCChip::reqIPI(uint64_t ipreq)
 void
 TsunamiCChip::postRTC()
 {
-    int size = tsunami->intrctrl->cpu->system->threadContexts.size();
+    int size = sys->threadContexts.size();
     assert(size <= Tsunami::Max_CPUs);
 
     for (int i = 0; i < size; i++) {
@@ -463,7 +463,7 @@ void
 TsunamiCChip::postDRIR(uint32_t interrupt)
 {
     uint64_t bitvector = ULL(1) << interrupt;
-    uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
+    uint64_t size = sys->threadContexts.size();
     assert(size <= Tsunami::Max_CPUs);
     drir |= bitvector;
 
@@ -481,7 +481,7 @@ void
 TsunamiCChip::clearDRIR(uint32_t interrupt)
 {
     uint64_t bitvector = ULL(1) << interrupt;
-    uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
+    uint64_t size = sys->threadContexts.size();
     assert(size <= Tsunami::Max_CPUs);
 
     if (drir & bitvector)