Moved the tsunami devices into the dev/alpha directory. Other devices "generic" devices are dependent on some of those files. That will either need to change, or most likely those devices will have to be considered architecture dependent.

--HG--
rename : src/dev/tsunami.cc => src/dev/alpha/tsunami.cc
rename : src/dev/tsunami.hh => src/dev/alpha/tsunami.hh
rename : src/dev/tsunami_cchip.cc => src/dev/alpha/tsunami_cchip.cc
rename : src/dev/tsunami_cchip.hh => src/dev/alpha/tsunami_cchip.hh
rename : src/dev/tsunami_io.cc => src/dev/alpha/tsunami_io.cc
rename : src/dev/tsunami_io.hh => src/dev/alpha/tsunami_io.hh
rename : src/dev/tsunami_pchip.cc => src/dev/alpha/tsunami_pchip.cc
rename : src/dev/tsunami_pchip.hh => src/dev/alpha/tsunami_pchip.hh
rename : src/dev/tsunamireg.h => src/dev/alpha/tsunamireg.h
extra : convert_revision : ffbb6fd93341d2623a6932bf096019b8976da694

10 files changed, 2703 insertions, 25 deletions

diff --git a/src/dev/alpha/SConscript b/src/dev/alpha/SConscript
index b4b879385..304cd9ca9 100644
--- a/src/dev/alpha/SConscript
+++ b/src/dev/alpha/SConscript
@@ -36,32 +36,32 @@ Import('env')
 
 sources = Split('''
 	console.cc
+	tsunami.cc
+	tsunami_cchip.cc
+	tsunami_io.cc
+	tsunami_fake.cc
+	tsunami_pchip.cc
 	''')
-#	dev/baddev.cc
-#	dev/disk_image.cc
-#	dev/etherbus.cc
-#	dev/etherdump.cc
-#	dev/etherint.cc
-#	dev/etherlink.cc
-#	dev/etherpkt.cc
-#	dev/ethertap.cc	
-#       dev/ide_ctrl.cc
-#	dev/ide_disk.cc
-#	dev/io_device.cc
-#	dev/isa_fake.cc
-#	dev/ns_gige.cc
-#	dev/pciconfigall.cc
-#	dev/pcidev.cc
-#	dev/pcifake.cc
-#	dev/pktfifo.cc
-#	dev/platform.cc
-#       dev/simconsole.cc
-#	dev/simple_disk.cc
-#	dev/tsunami.cc
-#	dev/tsunami_cchip.cc
-#	dev/tsunami_io.cc
-#	dev/tsunami_fake.cc
-#	dev/tsunami_pchip.cc
+#	baddev.cc
+#	disk_image.cc
+#	etherbus.cc
+#	etherdump.cc
+#	etherint.cc
+#	etherlink.cc
+#	etherpkt.cc
+#	ethertap.cc	
+#       ide_ctrl.cc
+#	ide_disk.cc
+#	io_device.cc
+#	isa_fake.cc
+#	ns_gige.cc
+#	pciconfigall.cc
+#	pcidev.cc
+#	pcifake.cc
+#	pktfifo.cc
+#	platform.cc
+#       simconsole.cc
+#	simple_disk.cc
 
 # Convert file names to SCons File objects.  This takes care of the
 # path relative to the top of the directory tree.
diff --git a/src/dev/alpha/tsunami.cc b/src/dev/alpha/tsunami.cc
new file mode 100644
index 000000000..608e88846
--- /dev/null
+++ b/src/dev/alpha/tsunami.cc
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * Implementation of Tsunami platform.
+ */
+
+#include <deque>
+#include <string>
+#include <vector>
+
+#include "cpu/intr_control.hh"
+#include "dev/simconsole.hh"
+#include "dev/alpha/tsunami_cchip.hh"
+#include "dev/alpha/tsunami_pchip.hh"
+#include "dev/alpha/tsunami_io.hh"
+#include "dev/alpha/tsunami.hh"
+#include "sim/builder.hh"
+#include "sim/system.hh"
+
+using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
+
+Tsunami::Tsunami(const string &name, System *s, IntrControl *ic)
+    : Platform(name, ic), system(s)
+{
+    // set the back pointer from the system to myself
+    system->platform = this;
+
+    for (int i = 0; i < Tsunami::Max_CPUs; i++)
+        intr_sum_type[i] = 0;
+}
+
+Tick
+Tsunami::intrFrequency()
+{
+    return io->frequency();
+}
+
+void
+Tsunami::postConsoleInt()
+{
+    io->postPIC(0x10);
+}
+
+void
+Tsunami::clearConsoleInt()
+{
+    io->clearPIC(0x10);
+}
+
+void
+Tsunami::postPciInt(int line)
+{
+    cchip->postDRIR(line);
+}
+
+void
+Tsunami::clearPciInt(int line)
+{
+    cchip->clearDRIR(line);
+}
+
+Addr
+Tsunami::pciToDma(Addr pciAddr) const
+{
+    return pchip->translatePciToDma(pciAddr);
+}
+
+
+Addr
+Tsunami::calcConfigAddr(int bus, int dev, int func)
+{
+   return pchip->calcConfigAddr(bus, dev, func);
+}
+
+void
+Tsunami::serialize(std::ostream &os)
+{
+    SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
+}
+
+void
+Tsunami::unserialize(Checkpoint *cp, const std::string &section)
+{
+    UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
+}
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
+
+    SimObjectParam<System *> system;
+    SimObjectParam<IntrControl *> intrctrl;
+
+END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
+
+    INIT_PARAM(system, "system"),
+    INIT_PARAM(intrctrl, "interrupt controller")
+
+END_INIT_SIM_OBJECT_PARAMS(Tsunami)
+
+CREATE_SIM_OBJECT(Tsunami)
+{
+    return new Tsunami(getInstanceName(), system, intrctrl);
+}
+
+REGISTER_SIM_OBJECT("Tsunami", Tsunami)
diff --git a/src/dev/alpha/tsunami.hh b/src/dev/alpha/tsunami.hh
new file mode 100644
index 000000000..6fbfac851
--- /dev/null
+++ b/src/dev/alpha/tsunami.hh
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/**
+ * @file
+ * Declaration of top level class for the Tsunami chipset. This class just
+ * retains pointers to all its children so the children can communicate.
+ */
+
+#ifndef __DEV_TSUNAMI_HH__
+#define __DEV_TSUNAMI_HH__
+
+#include "dev/platform.hh"
+
+class IdeController;
+class TsunamiCChip;
+class TsunamiPChip;
+class TsunamiIO;
+class System;
+
+/**
+  * Top level class for Tsunami Chipset emulation.
+  * This structure just contains pointers to all the
+  * children so the children can commnicate to do the
+  * read work
+  */
+
+class Tsunami : public Platform
+{
+  public:
+    /** Max number of CPUs in a Tsunami */
+    static const int Max_CPUs = 64;
+
+    /** Pointer to the system */
+    System *system;
+
+    /** Pointer to the TsunamiIO device which has the RTC */
+    TsunamiIO *io;
+
+    /** Pointer to the Tsunami CChip.
+     * The chip contains some configuration information and
+     * all the interrupt mask and status registers
+     */
+    TsunamiCChip *cchip;
+
+    /** Pointer to the Tsunami PChip.
+     * The pchip is the interface to the PCI bus, in our case
+     * it does not have to do much.
+     */
+    TsunamiPChip *pchip;
+
+    int intr_sum_type[Tsunami::Max_CPUs];
+    int ipi_pending[Tsunami::Max_CPUs];
+
+  public:
+    /**
+     * Constructor for the Tsunami Class.
+     * @param name name of the object
+     * @param s system the object belongs to
+     * @param intctrl pointer to the interrupt controller
+     */
+    Tsunami(const std::string &name, System *s, IntrControl *intctrl);
+
+    /**
+     * Return the interrupting frequency to AlphaAccess
+     * @return frequency of RTC interrupts
+     */
+    virtual Tick intrFrequency();
+
+    /**
+     * Cause the cpu to post a serial interrupt to the CPU.
+     */
+    virtual void postConsoleInt();
+
+    /**
+     * Clear a posted CPU interrupt (id=55)
+     */
+    virtual void clearConsoleInt();
+
+    /**
+     * Cause the chipset to post a cpi interrupt to the CPU.
+     */
+    virtual void postPciInt(int line);
+
+    /**
+     * Clear a posted PCI->CPU interrupt
+     */
+    virtual void clearPciInt(int line);
+
+
+    virtual Addr pciToDma(Addr pciAddr) const;
+
+    /**
+     * Calculate the configuration address given a bus/dev/func.
+     */
+    virtual Addr calcConfigAddr(int bus, int dev, int func);
+
+    /**
+     * Serialize this object to the given output stream.
+     * @param os The stream to serialize to.
+     */
+    virtual void serialize(std::ostream &os);
+
+    /**
+     * Reconstruct the state of this object from a checkpoint.
+     * @param cp The checkpoint use.
+     * @param section The section name of this object
+     */
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+};
+
+#endif // __DEV_TSUNAMI_HH__
diff --git a/src/dev/alpha/tsunami_cchip.cc b/src/dev/alpha/tsunami_cchip.cc
new file mode 100644
index 000000000..924e1d462
--- /dev/null
+++ b/src/dev/alpha/tsunami_cchip.cc
@@ -0,0 +1,555 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Ron Dreslinski
+ */
+
+/** @file
+ * Emulation of the Tsunami CChip CSRs
+ */
+
+#include <deque>
+#include <string>
+#include <vector>
+
+#include "arch/alpha/ev5.hh"
+#include "base/trace.hh"
+#include "cpu/intr_control.hh"
+#include "cpu/thread_context.hh"
+#include "dev/alpha/tsunami.hh"
+#include "dev/alpha/tsunami_cchip.hh"
+#include "dev/alpha/tsunamireg.h"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "mem/port.hh"
+#include "sim/builder.hh"
+#include "sim/system.hh"
+
+using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
+
+TsunamiCChip::TsunamiCChip(Params *p)
+    : BasicPioDevice(p), tsunami(p->tsunami)
+{
+    pioSize = 0xfffffff;
+
+    drir = 0;
+    ipint = 0;
+    itint = 0;
+
+    for (int x = 0; x < Tsunami::Max_CPUs; x++)
+    {
+        dim[x] = 0;
+        dir[x] = 0;
+    }
+
+    //Put back pointer in tsunami
+    tsunami->cchip = this;
+}
+
+Tick
+TsunamiCChip::read(PacketPtr pkt)
+{
+    DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
+
+    assert(pkt->result == Packet::Unknown);
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+
+    Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
+    Addr daddr = (pkt->getAddr() - pioAddr);
+
+    pkt->allocate();
+    switch (pkt->getSize()) {
+
+      case sizeof(uint64_t):
+          if (daddr & TSDEV_CC_BDIMS)
+          {
+              pkt->set(dim[(daddr >> 4) & 0x3F]);
+              break;
+          }
+
+          if (daddr & TSDEV_CC_BDIRS)
+          {
+              pkt->set(dir[(daddr >> 4) & 0x3F]);
+              break;
+          }
+
+          switch(regnum) {
+              case TSDEV_CC_CSR:
+                  pkt->set(0x0);
+                  break;
+              case TSDEV_CC_MTR:
+                  panic("TSDEV_CC_MTR not implemeted\n");
+                   break;
+              case TSDEV_CC_MISC:
+                  pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
+                                     (pkt->req->getCpuNum() & 0x3));
+                  break;
+              case TSDEV_CC_AAR0:
+              case TSDEV_CC_AAR1:
+              case TSDEV_CC_AAR2:
+              case TSDEV_CC_AAR3:
+                  pkt->set(0);
+                  break;
+              case TSDEV_CC_DIM0:
+                  pkt->set(dim[0]);
+                  break;
+              case TSDEV_CC_DIM1:
+                  pkt->set(dim[1]);
+                  break;
+              case TSDEV_CC_DIM2:
+                  pkt->set(dim[2]);
+                  break;
+              case TSDEV_CC_DIM3:
+                  pkt->set(dim[3]);
+                  break;
+              case TSDEV_CC_DIR0:
+                  pkt->set(dir[0]);
+                  break;
+              case TSDEV_CC_DIR1:
+                  pkt->set(dir[1]);
+                  break;
+              case TSDEV_CC_DIR2:
+                  pkt->set(dir[2]);
+                  break;
+              case TSDEV_CC_DIR3:
+                  pkt->set(dir[3]);
+                  break;
+              case TSDEV_CC_DRIR:
+                  pkt->set(drir);
+                  break;
+              case TSDEV_CC_PRBEN:
+                  panic("TSDEV_CC_PRBEN not implemented\n");
+                  break;
+              case TSDEV_CC_IIC0:
+              case TSDEV_CC_IIC1:
+              case TSDEV_CC_IIC2:
+              case TSDEV_CC_IIC3:
+                  panic("TSDEV_CC_IICx not implemented\n");
+                  break;
+              case TSDEV_CC_MPR0:
+              case TSDEV_CC_MPR1:
+              case TSDEV_CC_MPR2:
+              case TSDEV_CC_MPR3:
+                  panic("TSDEV_CC_MPRx not implemented\n");
+                  break;
+              case TSDEV_CC_IPIR:
+                  pkt->set(ipint);
+                  break;
+              case TSDEV_CC_ITIR:
+                  pkt->set(itint);
+                  break;
+              default:
+                  panic("default in cchip read reached, accessing 0x%x\n");
+           } // uint64_t
+
+      break;
+      case sizeof(uint32_t):
+      case sizeof(uint16_t):
+      case sizeof(uint8_t):
+      default:
+        panic("invalid access size(?) for tsunami register!\n");
+    }
+    DPRINTF(Tsunami, "Tsunami CChip: read  regnum=%#x size=%d data=%lld\n",
+            regnum, pkt->getSize(), pkt->get<uint64_t>());
+
+    pkt->result = Packet::Success;
+    return pioDelay;
+}
+
+Tick
+TsunamiCChip::write(PacketPtr pkt)
+{
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+    Addr daddr = pkt->getAddr() - pioAddr;
+    Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
+
+
+    assert(pkt->getSize() == sizeof(uint64_t));
+
+    DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
+
+    bool supportedWrite = false;
+
+
+    if (daddr & TSDEV_CC_BDIMS)
+    {
+        int number = (daddr >> 4) & 0x3F;
+
+        uint64_t bitvector;
+        uint64_t olddim;
+        uint64_t olddir;
+
+        olddim = dim[number];
+        olddir = dir[number];
+        dim[number] = pkt->get<uint64_t>();
+        dir[number] = dim[number] & drir;
+        for(int x = 0; x < Tsunami::Max_CPUs; x++)
+        {
+            bitvector = ULL(1) << x;
+            // Figure out which bits have changed
+            if ((dim[number] & bitvector) != (olddim & bitvector))
+            {
+                // The bit is now set and it wasn't before (set)
+                if((dim[number] & bitvector) && (dir[number] & bitvector))
+                {
+                    tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
+                    DPRINTF(Tsunami, "dim write resulting in posting dir"
+                            " interrupt to cpu %d\n", number);
+                }
+                else if ((olddir & bitvector) &&
+                        !(dir[number] & bitvector))
+                {
+                    // The bit was set and now its now clear and
+                    // we were interrupting on that bit before
+                    tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
+                    DPRINTF(Tsunami, "dim write resulting in clear"
+                            " dir interrupt to cpu %d\n", number);
+
+                }
+
+
+            }
+        }
+    } else {
+        switch(regnum) {
+          case TSDEV_CC_CSR:
+              panic("TSDEV_CC_CSR write\n");
+          case TSDEV_CC_MTR:
+              panic("TSDEV_CC_MTR write not implemented\n");
+          case TSDEV_CC_MISC:
+            uint64_t ipreq;
+            ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
+            //If it is bit 12-15, this is an IPI post
+            if (ipreq) {
+                reqIPI(ipreq);
+                supportedWrite = true;
+            }
+
+            //If it is bit 8-11, this is an IPI clear
+            uint64_t ipintr;
+            ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
+            if (ipintr) {
+                clearIPI(ipintr);
+                supportedWrite = true;
+            }
+
+            //If it is the 4-7th bit, clear the RTC interrupt
+            uint64_t itintr;
+              itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
+            if (itintr) {
+                  clearITI(itintr);
+                supportedWrite = true;
+            }
+
+              // ignore NXMs
+              if (pkt->get<uint64_t>() & 0x10000000)
+                  supportedWrite = true;
+
+            if(!supportedWrite)
+                  panic("TSDEV_CC_MISC write not implemented\n");
+
+            break;
+            case TSDEV_CC_AAR0:
+            case TSDEV_CC_AAR1:
+            case TSDEV_CC_AAR2:
+            case TSDEV_CC_AAR3:
+                panic("TSDEV_CC_AARx write not implemeted\n");
+            case TSDEV_CC_DIM0:
+            case TSDEV_CC_DIM1:
+            case TSDEV_CC_DIM2:
+            case TSDEV_CC_DIM3:
+                int number;
+                if(regnum == TSDEV_CC_DIM0)
+                    number = 0;
+                else if(regnum == TSDEV_CC_DIM1)
+                    number = 1;
+                else if(regnum == TSDEV_CC_DIM2)
+                    number = 2;
+                else
+                    number = 3;
+
+                uint64_t bitvector;
+                uint64_t olddim;
+                uint64_t olddir;
+
+                olddim = dim[number];
+                olddir = dir[number];
+                dim[number] = pkt->get<uint64_t>();
+                dir[number] = dim[number] & drir;
+                for(int x = 0; x < 64; x++)
+                {
+                    bitvector = ULL(1) << x;
+                    // Figure out which bits have changed
+                    if ((dim[number] & bitvector) != (olddim & bitvector))
+                    {
+                        // The bit is now set and it wasn't before (set)
+                        if((dim[number] & bitvector) && (dir[number] & bitvector))
+                        {
+                          tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
+                          DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
+                        }
+                        else if ((olddir & bitvector) &&
+                                !(dir[number] & bitvector))
+                        {
+                            // The bit was set and now its now clear and
+                            // we were interrupting on that bit before
+                            tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
+                          DPRINTF(Tsunami, "dim write resulting in clear"
+                                    " dir interrupt to cpu %d\n",
+                                    x);
+
+                        }
+
+
+                    }
+                }
+                break;
+            case TSDEV_CC_DIR0:
+            case TSDEV_CC_DIR1:
+            case TSDEV_CC_DIR2:
+            case TSDEV_CC_DIR3:
+                panic("TSDEV_CC_DIR write not implemented\n");
+            case TSDEV_CC_DRIR:
+                panic("TSDEV_CC_DRIR write not implemented\n");
+            case TSDEV_CC_PRBEN:
+                panic("TSDEV_CC_PRBEN write not implemented\n");
+            case TSDEV_CC_IIC0:
+            case TSDEV_CC_IIC1:
+            case TSDEV_CC_IIC2:
+            case TSDEV_CC_IIC3:
+                panic("TSDEV_CC_IICx write not implemented\n");
+            case TSDEV_CC_MPR0:
+            case TSDEV_CC_MPR1:
+            case TSDEV_CC_MPR2:
+            case TSDEV_CC_MPR3:
+                panic("TSDEV_CC_MPRx write not implemented\n");
+            case TSDEV_CC_IPIR:
+                clearIPI(pkt->get<uint64_t>());
+                break;
+            case TSDEV_CC_ITIR:
+                clearITI(pkt->get<uint64_t>());
+                break;
+            case TSDEV_CC_IPIQ:
+                reqIPI(pkt->get<uint64_t>());
+                break;
+            default:
+              panic("default in cchip read reached, accessing 0x%x\n");
+        }  // swtich(regnum)
+    } // not BIG_TSUNAMI write
+    pkt->result = Packet::Success;
+    return pioDelay;
+}
+
+void
+TsunamiCChip::clearIPI(uint64_t ipintr)
+{
+    int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
+    assert(numcpus <= Tsunami::Max_CPUs);
+
+    if (ipintr) {
+        for (int cpunum=0; cpunum < numcpus; cpunum++) {
+            // Check each cpu bit
+            uint64_t cpumask = ULL(1) << cpunum;
+            if (ipintr & cpumask) {
+                // Check if there is a pending ipi
+                if (ipint & cpumask) {
+                    ipint &= ~cpumask;
+                    tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
+                    DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
+                }
+                else
+                    warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
+            }
+        }
+    }
+    else
+        panic("Big IPI Clear, but not processors indicated\n");
+}
+
+void
+TsunamiCChip::clearITI(uint64_t itintr)
+{
+    int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
+    assert(numcpus <= Tsunami::Max_CPUs);
+
+    if (itintr) {
+        for (int i=0; i < numcpus; i++) {
+            uint64_t cpumask = ULL(1) << i;
+            if (itintr & cpumask & itint) {
+                tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
+                itint &= ~cpumask;
+                DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
+            }
+        }
+    }
+    else
+        panic("Big ITI Clear, but not processors indicated\n");
+}
+
+void
+TsunamiCChip::reqIPI(uint64_t ipreq)
+{
+    int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
+    assert(numcpus <= Tsunami::Max_CPUs);
+
+    if (ipreq) {
+        for (int cpunum=0; cpunum < numcpus; cpunum++) {
+            // Check each cpu bit
+            uint64_t cpumask = ULL(1) << cpunum;
+            if (ipreq & cpumask) {
+                // Check if there is already an ipi (bits 8:11)
+                if (!(ipint & cpumask)) {
+                    ipint  |= cpumask;
+                    tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
+                    DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
+                }
+                else
+                    warn("post IPI for CPU=%d, but IPI already\n", cpunum);
+            }
+        }
+    }
+    else
+        panic("Big IPI Request, but not processors indicated\n");
+}
+
+
+void
+TsunamiCChip::postRTC()
+{
+    int size = tsunami->intrctrl->cpu->system->threadContexts.size();
+    assert(size <= Tsunami::Max_CPUs);
+
+    for (int i = 0; i < size; i++) {
+        uint64_t cpumask = ULL(1) << i;
+       if (!(cpumask & itint)) {
+           itint |= cpumask;
+           tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
+           DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i);
+       }
+    }
+
+}
+
+void
+TsunamiCChip::postDRIR(uint32_t interrupt)
+{
+    uint64_t bitvector = ULL(1) << interrupt;
+    uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
+    assert(size <= Tsunami::Max_CPUs);
+    drir |= bitvector;
+
+    for(int i=0; i < size; i++) {
+        dir[i] = dim[i] & drir;
+       if (dim[i] & bitvector) {
+              tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
+              DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
+                        "interrupt %d\n",i, interrupt);
+       }
+    }
+}
+
+void
+TsunamiCChip::clearDRIR(uint32_t interrupt)
+{
+    uint64_t bitvector = ULL(1) << interrupt;
+    uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
+    assert(size <= Tsunami::Max_CPUs);
+
+    if (drir & bitvector)
+    {
+        drir &= ~bitvector;
+        for(int i=0; i < size; i++) {
+           if (dir[i] & bitvector) {
+               tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
+               DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
+                    "interrupt %d\n",i, interrupt);
+
+           }
+           dir[i] = dim[i] & drir;
+        }
+    }
+    else
+        DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
+}
+
+
+void
+TsunamiCChip::serialize(std::ostream &os)
+{
+    SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
+    SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
+    SERIALIZE_SCALAR(ipint);
+    SERIALIZE_SCALAR(itint);
+    SERIALIZE_SCALAR(drir);
+}
+
+void
+TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
+{
+    UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
+    UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
+    UNSERIALIZE_SCALAR(ipint);
+    UNSERIALIZE_SCALAR(itint);
+    UNSERIALIZE_SCALAR(drir);
+}
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
+
+    Param<Addr> pio_addr;
+    Param<Tick> pio_latency;
+    SimObjectParam<Platform *> platform;
+    SimObjectParam<System *> system;
+    SimObjectParam<Tsunami *> tsunami;
+
+END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
+
+    INIT_PARAM(pio_addr, "Device Address"),
+    INIT_PARAM(pio_latency, "Programmed IO latency"),
+    INIT_PARAM(platform, "platform"),
+    INIT_PARAM(system, "system object"),
+    INIT_PARAM(tsunami, "Tsunami")
+
+END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
+
+CREATE_SIM_OBJECT(TsunamiCChip)
+{
+    TsunamiCChip::Params *p = new TsunamiCChip::Params;
+    p->name = getInstanceName();
+    p->pio_addr = pio_addr;
+    p->pio_delay = pio_latency;
+    p->platform = platform;
+    p->system = system;
+    p->tsunami = tsunami;
+    return new TsunamiCChip(p);
+}
+
+REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
diff --git a/src/dev/alpha/tsunami_cchip.hh b/src/dev/alpha/tsunami_cchip.hh
new file mode 100644
index 000000000..004c3cd29
--- /dev/null
+++ b/src/dev/alpha/tsunami_cchip.hh
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * Emulation of the Tsunami CChip CSRs
+ */
+
+#ifndef __TSUNAMI_CCHIP_HH__
+#define __TSUNAMI_CCHIP_HH__
+
+#include "dev/alpha/tsunami.hh"
+#include "base/range.hh"
+#include "dev/io_device.hh"
+
+
+/**
+ * Tsunami CChip CSR Emulation. This device includes all the interrupt
+ * handling code for the chipset.
+ */
+class TsunamiCChip : public BasicPioDevice
+{
+  protected:
+    /**
+     * pointer to the tsunami object.
+     * This is our access to all the other tsunami
+     * devices.
+     */
+    Tsunami *tsunami;
+
+    /**
+     * The dims are device interrupt mask registers.
+     * One exists for each CPU, the DRIR X DIM = DIR
+     */
+    uint64_t dim[Tsunami::Max_CPUs];
+
+    /**
+     * The dirs are device interrupt registers.
+     * One exists for each CPU, the DRIR X DIM = DIR
+     */
+    uint64_t dir[Tsunami::Max_CPUs];
+
+    /**
+     * This register contains bits for each PCI interrupt
+     * that can occur.
+     */
+    uint64_t drir;
+
+    /** Indicator of which CPUs have an IPI interrupt */
+    uint64_t ipint;
+
+    /** Indicator of which CPUs have an RTC interrupt */
+    uint64_t itint;
+
+  public:
+    struct Params : public BasicPioDevice::Params
+    {
+        Tsunami *tsunami;
+    };
+  protected:
+    const Params *params() const {return (const Params *)_params; }
+
+  public:
+    /**
+     * Initialize the Tsunami CChip by setting all of the
+     * device register to 0.
+     * @param p params struct
+     */
+    TsunamiCChip(Params *p);
+
+    virtual Tick read(PacketPtr pkt);
+
+    virtual Tick write(PacketPtr pkt);
+
+    /**
+     * post an RTC interrupt to the CPU
+     */
+    void postRTC();
+
+    /**
+     * post an interrupt to the CPU.
+     * @param interrupt the interrupt number to post (0-64)
+     */
+    void postDRIR(uint32_t interrupt);
+
+    /**
+     * clear an interrupt previously posted to the CPU.
+     * @param interrupt the interrupt number to post (0-64)
+     */
+    void clearDRIR(uint32_t interrupt);
+
+    /**
+     * post an ipi interrupt  to the CPU.
+     * @param ipintr the cpu number to clear(bitvector)
+     */
+    void clearIPI(uint64_t ipintr);
+
+    /**
+     * clear a timer interrupt previously posted to the CPU.
+     * @param itintr the cpu number to clear(bitvector)
+     */
+    void clearITI(uint64_t itintr);
+
+    /**
+     * request an interrupt be posted to the CPU.
+     * @param ipreq the cpu number to interrupt(bitvector)
+     */
+    void reqIPI(uint64_t ipreq);
+
+
+    /**
+     * Serialize this object to the given output stream.
+     * @param os The stream to serialize to.
+     */
+    virtual void serialize(std::ostream &os);
+
+    /**
+     * Reconstruct the state of this object from a checkpoint.
+     * @param cp The checkpoint use.
+     * @param section The section name of this object
+     */
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+};
+
+#endif // __TSUNAMI_CCHIP_HH__
diff --git a/src/dev/alpha/tsunami_io.cc b/src/dev/alpha/tsunami_io.cc
new file mode 100644
index 000000000..def214a95
--- /dev/null
+++ b/src/dev/alpha/tsunami_io.cc
@@ -0,0 +1,688 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Andrew Schultz
+ *          Miguel Serrano
+ */
+
+/** @file
+ * Tsunami I/O including PIC, PIT, RTC, DMA
+ */
+
+#include <sys/time.h>
+
+#include <deque>
+#include <string>
+#include <vector>
+
+#include "base/trace.hh"
+#include "dev/pitreg.h"
+#include "dev/rtcreg.h"
+#include "dev/alpha/tsunami_cchip.hh"
+#include "dev/alpha/tsunami.hh"
+#include "dev/alpha/tsunami_io.hh"
+#include "dev/alpha/tsunamireg.h"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "mem/port.hh"
+#include "sim/builder.hh"
+#include "sim/system.hh"
+
+using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
+
+TsunamiIO::RTC::RTC(const string &name, Tsunami* t, Tick i)
+    : _name(name), event(t, i), addr(0)
+{
+    memset(clock_data, 0, sizeof(clock_data));
+    stat_regA = RTCA_32768HZ | RTCA_1024HZ;
+    stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR;
+}
+
+void
+TsunamiIO::RTC::set_time(time_t t)
+{
+    struct tm tm;
+    gmtime_r(&t, &tm);
+
+    sec = tm.tm_sec;
+    min = tm.tm_min;
+    hour = tm.tm_hour;
+    wday = tm.tm_wday + 1;
+    mday = tm.tm_mday;
+    mon = tm.tm_mon + 1;
+    year = tm.tm_year;
+
+    DPRINTFN("Real-time clock set to %s", asctime(&tm));
+}
+
+void
+TsunamiIO::RTC::writeAddr(const uint8_t data)
+{
+    if (data <= RTC_STAT_REGD)
+        addr = data;
+    else
+        panic("RTC addresses over 0xD are not implemented.\n");
+}
+
+void
+TsunamiIO::RTC::writeData(const uint8_t data)
+{
+    if (addr < RTC_STAT_REGA)
+        clock_data[addr] = data;
+    else {
+        switch (addr) {
+          case RTC_STAT_REGA:
+            if (data != (RTCA_32768HZ | RTCA_1024HZ))
+                panic("Unimplemented RTC register A value write!\n");
+            stat_regA = data;
+            break;
+          case RTC_STAT_REGB:
+            if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR))
+                panic("Write to RTC reg B bits that are not implemented!\n");
+
+            if (data & RTCB_PRDC_IE) {
+                if (!event.scheduled())
+                    event.scheduleIntr();
+            } else {
+                if (event.scheduled())
+                    event.deschedule();
+            }
+            stat_regB = data;
+            break;
+          case RTC_STAT_REGC:
+          case RTC_STAT_REGD:
+            panic("RTC status registers C and D are not implemented.\n");
+            break;
+        }
+    }
+}
+
+uint8_t
+TsunamiIO::RTC::readData()
+{
+    if (addr < RTC_STAT_REGA)
+        return clock_data[addr];
+    else {
+        switch (addr) {
+          case RTC_STAT_REGA:
+            // toggle UIP bit for linux
+            stat_regA ^= RTCA_UIP;
+            return stat_regA;
+            break;
+          case RTC_STAT_REGB:
+            return stat_regB;
+            break;
+          case RTC_STAT_REGC:
+          case RTC_STAT_REGD:
+            return 0x00;
+            break;
+          default:
+            panic("Shouldn't be here");
+        }
+    }
+}
+
+void
+TsunamiIO::RTC::serialize(const string &base, ostream &os)
+{
+    paramOut(os, base + ".addr", addr);
+    arrayParamOut(os, base + ".clock_data", clock_data, sizeof(clock_data));
+    paramOut(os, base + ".stat_regA", stat_regA);
+    paramOut(os, base + ".stat_regB", stat_regB);
+}
+
+void
+TsunamiIO::RTC::unserialize(const string &base, Checkpoint *cp,
+                            const string &section)
+{
+    paramIn(cp, section, base + ".addr", addr);
+    arrayParamIn(cp, section, base + ".clock_data", clock_data,
+                 sizeof(clock_data));
+    paramIn(cp, section, base + ".stat_regA", stat_regA);
+    paramIn(cp, section, base + ".stat_regB", stat_regB);
+
+    // We're not unserializing the event here, but we need to
+    // rescehedule the event since curTick was moved forward by the
+    // checkpoint
+    event.reschedule(curTick + event.interval);
+}
+
+TsunamiIO::RTC::RTCEvent::RTCEvent(Tsunami*t, Tick i)
+    : Event(&mainEventQueue), tsunami(t), interval(i)
+{
+    DPRINTF(MC146818, "RTC Event Initilizing\n");
+    schedule(curTick + interval);
+}
+
+void
+TsunamiIO::RTC::RTCEvent::scheduleIntr()
+{
+  schedule(curTick + interval);
+}
+
+void
+TsunamiIO::RTC::RTCEvent::process()
+{
+    DPRINTF(MC146818, "RTC Timer Interrupt\n");
+    schedule(curTick + interval);
+    //Actually interrupt the processor here
+    tsunami->cchip->postRTC();
+}
+
+const char *
+TsunamiIO::RTC::RTCEvent::description()
+{
+    return "tsunami RTC interrupt";
+}
+
+TsunamiIO::PITimer::PITimer(const string &name)
+    : _name(name), counter0(name + ".counter0"), counter1(name + ".counter1"),
+      counter2(name + ".counter2")
+{
+    counter[0] = &counter0;
+    counter[1] = &counter0;
+    counter[2] = &counter0;
+}
+
+void
+TsunamiIO::PITimer::writeControl(const uint8_t data)
+{
+    int rw;
+    int sel;
+
+    sel = GET_CTRL_SEL(data);
+
+    if (sel == PIT_READ_BACK)
+       panic("PITimer Read-Back Command is not implemented.\n");
+
+    rw = GET_CTRL_RW(data);
+
+    if (rw == PIT_RW_LATCH_COMMAND)
+        counter[sel]->latchCount();
+    else {
+        counter[sel]->setRW(rw);
+        counter[sel]->setMode(GET_CTRL_MODE(data));
+        counter[sel]->setBCD(GET_CTRL_BCD(data));
+    }
+}
+
+void
+TsunamiIO::PITimer::serialize(const string &base, ostream &os)
+{
+    // serialize the counters
+    counter0.serialize(base + ".counter0", os);
+    counter1.serialize(base + ".counter1", os);
+    counter2.serialize(base + ".counter2", os);
+}
+
+void
+TsunamiIO::PITimer::unserialize(const string &base, Checkpoint *cp,
+                                const string &section)
+{
+    // unserialze the counters
+    counter0.unserialize(base + ".counter0", cp, section);
+    counter1.unserialize(base + ".counter1", cp, section);
+    counter2.unserialize(base + ".counter2", cp, section);
+}
+
+TsunamiIO::PITimer::Counter::Counter(const string &name)
+    : _name(name), event(this), count(0), latched_count(0), period(0),
+      mode(0), output_high(false), latch_on(false), read_byte(LSB),
+      write_byte(LSB)
+{
+
+}
+
+void
+TsunamiIO::PITimer::Counter::latchCount()
+{
+    // behave like a real latch
+    if(!latch_on) {
+        latch_on = true;
+        read_byte = LSB;
+        latched_count = count;
+    }
+}
+
+uint8_t
+TsunamiIO::PITimer::Counter::read()
+{
+    if (latch_on) {
+        switch (read_byte) {
+          case LSB:
+            read_byte = MSB;
+            return (uint8_t)latched_count;
+            break;
+          case MSB:
+            read_byte = LSB;
+            latch_on = false;
+            return latched_count >> 8;
+            break;
+          default:
+            panic("Shouldn't be here");
+        }
+    } else {
+        switch (read_byte) {
+          case LSB:
+            read_byte = MSB;
+            return (uint8_t)count;
+            break;
+          case MSB:
+            read_byte = LSB;
+            return count >> 8;
+            break;
+          default:
+            panic("Shouldn't be here");
+        }
+    }
+}
+
+void
+TsunamiIO::PITimer::Counter::write(const uint8_t data)
+{
+    switch (write_byte) {
+      case LSB:
+        count = (count & 0xFF00) | data;
+
+        if (event.scheduled())
+          event.deschedule();
+        output_high = false;
+        write_byte = MSB;
+        break;
+
+      case MSB:
+        count = (count & 0x00FF) | (data << 8);
+        period = count;
+
+        if (period > 0) {
+            DPRINTF(Tsunami, "Timer set to curTick + %d\n",
+                    count * event.interval);
+            event.schedule(curTick + count * event.interval);
+        }
+        write_byte = LSB;
+        break;
+    }
+}
+
+void
+TsunamiIO::PITimer::Counter::setRW(int rw_val)
+{
+    if (rw_val != PIT_RW_16BIT)
+        panic("Only LSB/MSB read/write is implemented.\n");
+}
+
+void
+TsunamiIO::PITimer::Counter::setMode(int mode_val)
+{
+    if(mode_val != PIT_MODE_INTTC && mode_val != PIT_MODE_RATEGEN &&
+       mode_val != PIT_MODE_SQWAVE)
+        panic("PIT mode %#x is not implemented: \n", mode_val);
+
+    mode = mode_val;
+}
+
+void
+TsunamiIO::PITimer::Counter::setBCD(int bcd_val)
+{
+    if (bcd_val != PIT_BCD_FALSE)
+        panic("PITimer does not implement BCD counts.\n");
+}
+
+bool
+TsunamiIO::PITimer::Counter::outputHigh()
+{
+    return output_high;
+}
+
+void
+TsunamiIO::PITimer::Counter::serialize(const string &base, ostream &os)
+{
+    paramOut(os, base + ".count", count);
+    paramOut(os, base + ".latched_count", latched_count);
+    paramOut(os, base + ".period", period);
+    paramOut(os, base + ".mode", mode);
+    paramOut(os, base + ".output_high", output_high);
+    paramOut(os, base + ".latch_on", latch_on);
+    paramOut(os, base + ".read_byte", read_byte);
+    paramOut(os, base + ".write_byte", write_byte);
+
+    Tick event_tick = 0;
+    if (event.scheduled())
+        event_tick = event.when();
+    paramOut(os, base + ".event_tick", event_tick);
+}
+
+void
+TsunamiIO::PITimer::Counter::unserialize(const string &base, Checkpoint *cp,
+                                         const string &section)
+{
+    paramIn(cp, section, base + ".count", count);
+    paramIn(cp, section, base + ".latched_count", latched_count);
+    paramIn(cp, section, base + ".period", period);
+    paramIn(cp, section, base + ".mode", mode);
+    paramIn(cp, section, base + ".output_high", output_high);
+    paramIn(cp, section, base + ".latch_on", latch_on);
+    paramIn(cp, section, base + ".read_byte", read_byte);
+    paramIn(cp, section, base + ".write_byte", write_byte);
+
+    Tick event_tick;
+    paramIn(cp, section, base + ".event_tick", event_tick);
+    if (event_tick)
+        event.schedule(event_tick);
+}
+
+TsunamiIO::PITimer::Counter::CounterEvent::CounterEvent(Counter* c_ptr)
+    : Event(&mainEventQueue)
+{
+    interval = (Tick)(Clock::Float::s / 1193180.0);
+    counter = c_ptr;
+}
+
+void
+TsunamiIO::PITimer::Counter::CounterEvent::process()
+{
+    DPRINTF(Tsunami, "Timer Interrupt\n");
+    switch (counter->mode) {
+      case PIT_MODE_INTTC:
+        counter->output_high = true;
+      case PIT_MODE_RATEGEN:
+      case PIT_MODE_SQWAVE:
+        break;
+      default:
+        panic("Unimplemented PITimer mode.\n");
+    }
+}
+
+const char *
+TsunamiIO::PITimer::Counter::CounterEvent::description()
+{
+    return "tsunami 8254 Interval timer";
+}
+
+TsunamiIO::TsunamiIO(Params *p)
+    : BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"),
+      rtc(p->name + ".rtc", p->tsunami, p->frequency)
+{
+    pioSize = 0xff;
+
+    // set the back pointer from tsunami to myself
+    tsunami->io = this;
+
+    timerData = 0;
+    rtc.set_time(p->init_time == 0 ? time(NULL) : p->init_time);
+    picr = 0;
+    picInterrupting = false;
+}
+
+Tick
+TsunamiIO::frequency() const
+{
+    return Clock::Frequency / params()->frequency;
+}
+
+Tick
+TsunamiIO::read(PacketPtr pkt)
+{
+    assert(pkt->result == Packet::Unknown);
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+
+    Addr daddr = pkt->getAddr() - pioAddr;
+
+    DPRINTF(Tsunami, "io read  va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(),
+            pkt->getSize(), daddr);
+
+    pkt->allocate();
+
+    if (pkt->getSize() == sizeof(uint8_t)) {
+        switch(daddr) {
+          // PIC1 mask read
+          case TSDEV_PIC1_MASK:
+            pkt->set(~mask1);
+            break;
+          case TSDEV_PIC2_MASK:
+            pkt->set(~mask2);
+            break;
+          case TSDEV_PIC1_ISR:
+              // !!! If this is modified 64bit case needs to be too
+              // Pal code has to do a 64 bit physical read because there is
+              // no load physical byte instruction
+              pkt->set(picr);
+              break;
+          case TSDEV_PIC2_ISR:
+              // PIC2 not implemnted... just return 0
+              pkt->set(0x00);
+              break;
+          case TSDEV_TMR0_DATA:
+            pkt->set(pitimer.counter0.read());
+            break;
+          case TSDEV_TMR1_DATA:
+            pkt->set(pitimer.counter1.read());
+            break;
+          case TSDEV_TMR2_DATA:
+            pkt->set(pitimer.counter2.read());
+            break;
+          case TSDEV_RTC_DATA:
+            pkt->set(rtc.readData());
+            break;
+          case TSDEV_CTRL_PORTB:
+            if (pitimer.counter2.outputHigh())
+                pkt->set(PORTB_SPKR_HIGH);
+            else
+                pkt->set(0x00);
+            break;
+          default:
+            panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize());
+        }
+    } else if (pkt->getSize() == sizeof(uint64_t)) {
+        if (daddr == TSDEV_PIC1_ISR)
+            pkt->set<uint64_t>(picr);
+        else
+           panic("I/O Read - invalid addr - va %#x size %d\n",
+                   pkt->getAddr(), pkt->getSize());
+    } else {
+       panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize());
+    }
+    pkt->result = Packet::Success;
+    return pioDelay;
+}
+
+Tick
+TsunamiIO::write(PacketPtr pkt)
+{
+    assert(pkt->result == Packet::Unknown);
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+    Addr daddr = pkt->getAddr() - pioAddr;
+
+    DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
+            pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get<uint8_t>());
+
+    assert(pkt->getSize() == sizeof(uint8_t));
+
+    switch(daddr) {
+      case TSDEV_PIC1_MASK:
+        mask1 = ~(pkt->get<uint8_t>());
+        if ((picr & mask1) && !picInterrupting) {
+            picInterrupting = true;
+            tsunami->cchip->postDRIR(55);
+            DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
+        }
+        if ((!(picr & mask1)) && picInterrupting) {
+            picInterrupting = false;
+            tsunami->cchip->clearDRIR(55);
+            DPRINTF(Tsunami, "clearing pic interrupt\n");
+        }
+        break;
+      case TSDEV_PIC2_MASK:
+        mask2 = pkt->get<uint8_t>();
+        //PIC2 Not implemented to interrupt
+        break;
+      case TSDEV_PIC1_ACK:
+        // clear the interrupt on the PIC
+        picr &= ~(1 << (pkt->get<uint8_t>() & 0xF));
+        if (!(picr & mask1))
+            tsunami->cchip->clearDRIR(55);
+        break;
+      case TSDEV_DMA1_MODE:
+        mode1 = pkt->get<uint8_t>();
+        break;
+      case TSDEV_DMA2_MODE:
+        mode2 = pkt->get<uint8_t>();
+        break;
+      case TSDEV_TMR0_DATA:
+        pitimer.counter0.write(pkt->get<uint8_t>());
+        break;
+      case TSDEV_TMR1_DATA:
+        pitimer.counter1.write(pkt->get<uint8_t>());
+        break;
+      case TSDEV_TMR2_DATA:
+        pitimer.counter2.write(pkt->get<uint8_t>());
+        break;
+      case TSDEV_TMR_CTRL:
+        pitimer.writeControl(pkt->get<uint8_t>());
+        break;
+      case TSDEV_RTC_ADDR:
+        rtc.writeAddr(pkt->get<uint8_t>());
+        break;
+      case TSDEV_RTC_DATA:
+        rtc.writeData(pkt->get<uint8_t>());
+        break;
+      case TSDEV_KBD:
+      case TSDEV_DMA1_CMND:
+      case TSDEV_DMA2_CMND:
+      case TSDEV_DMA1_MMASK:
+      case TSDEV_DMA2_MMASK:
+      case TSDEV_PIC2_ACK:
+      case TSDEV_DMA1_RESET:
+      case TSDEV_DMA2_RESET:
+      case TSDEV_DMA1_MASK:
+      case TSDEV_DMA2_MASK:
+      case TSDEV_CTRL_PORTB:
+        break;
+      default:
+        panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>());
+    }
+
+    pkt->result = Packet::Success;
+    return pioDelay;
+}
+
+void
+TsunamiIO::postPIC(uint8_t bitvector)
+{
+    //PIC2 Is not implemented, because nothing of interest there
+    picr |= bitvector;
+    if (picr & mask1) {
+        tsunami->cchip->postDRIR(55);
+        DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
+    }
+}
+
+void
+TsunamiIO::clearPIC(uint8_t bitvector)
+{
+    //PIC2 Is not implemented, because nothing of interest there
+    picr &= ~bitvector;
+    if (!(picr & mask1)) {
+        tsunami->cchip->clearDRIR(55);
+        DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
+    }
+}
+
+void
+TsunamiIO::serialize(ostream &os)
+{
+    SERIALIZE_SCALAR(timerData);
+    SERIALIZE_SCALAR(mask1);
+    SERIALIZE_SCALAR(mask2);
+    SERIALIZE_SCALAR(mode1);
+    SERIALIZE_SCALAR(mode2);
+    SERIALIZE_SCALAR(picr);
+    SERIALIZE_SCALAR(picInterrupting);
+
+    // Serialize the timers
+    pitimer.serialize("pitimer", os);
+    rtc.serialize("rtc", os);
+}
+
+void
+TsunamiIO::unserialize(Checkpoint *cp, const string &section)
+{
+    UNSERIALIZE_SCALAR(timerData);
+    UNSERIALIZE_SCALAR(mask1);
+    UNSERIALIZE_SCALAR(mask2);
+    UNSERIALIZE_SCALAR(mode1);
+    UNSERIALIZE_SCALAR(mode2);
+    UNSERIALIZE_SCALAR(picr);
+    UNSERIALIZE_SCALAR(picInterrupting);
+
+    // Unserialize the timers
+    pitimer.unserialize("pitimer", cp, section);
+    rtc.unserialize("rtc", cp, section);
+}
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
+
+    Param<Addr> pio_addr;
+    Param<Tick> pio_latency;
+    Param<Tick> frequency;
+    SimObjectParam<Platform *> platform;
+    SimObjectParam<System *> system;
+    Param<time_t> time;
+    SimObjectParam<Tsunami *> tsunami;
+
+END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
+
+    INIT_PARAM(pio_addr, "Device Address"),
+    INIT_PARAM(pio_latency, "Programmed IO latency"),
+    INIT_PARAM(frequency, "clock interrupt frequency"),
+    INIT_PARAM(platform, "platform"),
+    INIT_PARAM(system, "system object"),
+    INIT_PARAM(time, "System time to use (0 for actual time"),
+    INIT_PARAM(tsunami, "Tsunami")
+
+END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
+
+CREATE_SIM_OBJECT(TsunamiIO)
+{
+    TsunamiIO::Params *p = new TsunamiIO::Params;
+    p->frequency = frequency;
+    p->name = getInstanceName();
+    p->pio_addr = pio_addr;
+    p->pio_delay = pio_latency;
+    p->platform = platform;
+    p->system = system;
+    p->init_time = time;
+    p->tsunami = tsunami;
+    return new TsunamiIO(p);
+}
+
+REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)
diff --git a/src/dev/alpha/tsunami_io.hh b/src/dev/alpha/tsunami_io.hh
new file mode 100644
index 000000000..54acefc25
--- /dev/null
+++ b/src/dev/alpha/tsunami_io.hh
@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Andrew Schultz
+ *          Miguel Serrano
+ */
+
+/** @file
+ * Tsunami I/O Space mapping including RTC/timer interrupts
+ */
+
+#ifndef __DEV_TSUNAMI_IO_HH__
+#define __DEV_TSUNAMI_IO_HH__
+
+#include "dev/io_device.hh"
+#include "base/range.hh"
+#include "dev/alpha/tsunami.hh"
+#include "sim/eventq.hh"
+
+/**
+ * Tsunami I/O device is a catch all for all the south bridge stuff we care
+ * to implement.
+ */
+class TsunamiIO : public BasicPioDevice
+{
+  private:
+    struct tm tm;
+
+  protected:
+    /** Real-Time Clock (MC146818) */
+    class RTC
+    {
+      private:
+        /** Event for RTC periodic interrupt */
+        struct RTCEvent : public Event
+        {
+            /** A pointer back to tsunami to create interrupt the processor. */
+            Tsunami* tsunami;
+            Tick interval;
+
+            RTCEvent(Tsunami* t, Tick i);
+
+            /** Schedule the RTC periodic interrupt */
+            void scheduleIntr();
+
+            /** Event process to occur at interrupt*/
+            virtual void process();
+
+            /** Event description */
+            virtual const char *description();
+        };
+
+      private:
+        std::string _name;
+        const std::string &name() const { return _name; }
+
+        /** RTC periodic interrupt event */
+        RTCEvent event;
+
+        /** Current RTC register address/index */
+        int addr;
+
+        /** Data for real-time clock function */
+        union {
+            uint8_t clock_data[10];
+
+            struct {
+                uint8_t sec;
+                uint8_t sec_alrm;
+                uint8_t min;
+                uint8_t min_alrm;
+                uint8_t hour;
+                uint8_t hour_alrm;
+                uint8_t wday;
+                uint8_t mday;
+                uint8_t mon;
+                uint8_t year;
+            };
+        };
+
+        /** RTC status register A */
+        uint8_t stat_regA;
+
+        /** RTC status register B */
+        uint8_t stat_regB;
+
+      public:
+        RTC(const std::string &name, Tsunami* t, Tick i);
+
+        /** Set the initial RTC time/date */
+        void set_time(time_t t);
+
+        /** RTC address port: write address of RTC RAM data to access */
+        void writeAddr(const uint8_t data);
+
+        /** RTC write data */
+        void writeData(const uint8_t data);
+
+        /** RTC read data */
+        uint8_t readData();
+
+        /**
+          * Serialize this object to the given output stream.
+          * @param base The base name of the counter object.
+          * @param os The stream to serialize to.
+          */
+        void serialize(const std::string &base, std::ostream &os);
+
+        /**
+         * Reconstruct the state of this object from a checkpoint.
+          * @param base The base name of the counter object.
+         * @param cp The checkpoint use.
+         * @param section The section name of this object
+         */
+        void unserialize(const std::string &base, Checkpoint *cp,
+                         const std::string &section);
+    };
+
+    /** Programmable Interval Timer (Intel 8254) */
+    class PITimer
+    {
+        /** Counter element for PIT */
+        class Counter
+        {
+            /** Event for counter interrupt */
+            class CounterEvent : public Event
+            {
+              private:
+                /** Pointer back to Counter */
+                Counter* counter;
+                Tick interval;
+
+              public:
+                CounterEvent(Counter*);
+
+                /** Event process */
+                virtual void process();
+
+                /** Event description */
+                virtual const char *description();
+
+                friend class Counter;
+            };
+
+          private:
+            std::string _name;
+            const std::string &name() const { return _name; }
+
+            CounterEvent event;
+
+            /** Current count value */
+            uint16_t count;
+
+            /** Latched count */
+            uint16_t latched_count;
+
+            /** Interrupt period */
+            uint16_t period;
+
+            /** Current mode of operation */
+            uint8_t mode;
+
+            /** Output goes high when the counter reaches zero */
+            bool output_high;
+
+            /** State of the count latch */
+            bool latch_on;
+
+            /** Set of values for read_byte and write_byte */
+            enum {LSB, MSB};
+
+            /** Determine which byte of a 16-bit count value to read/write */
+            uint8_t read_byte, write_byte;
+
+          public:
+            Counter(const std::string &name);
+
+            /** Latch the current count (if one is not already latched) */
+            void latchCount();
+
+            /** Set the read/write mode */
+            void setRW(int rw_val);
+
+            /** Set operational mode */
+            void setMode(int mode_val);
+
+            /** Set count encoding */
+            void setBCD(int bcd_val);
+
+            /** Read a count byte */
+            uint8_t read();
+
+            /** Write a count byte */
+            void write(const uint8_t data);
+
+            /** Is the output high? */
+            bool outputHigh();
+
+            /**
+             * Serialize this object to the given output stream.
+             * @param base The base name of the counter object.
+             * @param os   The stream to serialize to.
+             */
+            void serialize(const std::string &base, std::ostream &os);
+
+            /**
+             * Reconstruct the state of this object from a checkpoint.
+             * @param base The base name of the counter object.
+             * @param cp The checkpoint use.
+             * @param section The section name of this object
+             */
+            void unserialize(const std::string &base, Checkpoint *cp,
+                             const std::string &section);
+        };
+
+      private:
+        std::string _name;
+        const std::string &name() const { return _name; }
+
+        /** PIT has three seperate counters */
+        Counter *counter[3];
+
+      public:
+        /** Public way to access individual counters (avoid array accesses) */
+        Counter counter0;
+        Counter counter1;
+        Counter counter2;
+
+        PITimer(const std::string &name);
+
+        /** Write control word */
+        void writeControl(const uint8_t data);
+
+        /**
+         * Serialize this object to the given output stream.
+         * @param base The base name of the counter object.
+         * @param os The stream to serialize to.
+         */
+        void serialize(const std::string &base, std::ostream &os);
+
+        /**
+         * Reconstruct the state of this object from a checkpoint.
+         * @param base The base name of the counter object.
+         * @param cp The checkpoint use.
+         * @param section The section name of this object
+         */
+        void unserialize(const std::string &base, Checkpoint *cp,
+                         const std::string &section);
+    };
+
+    /** Mask of the PIC1 */
+    uint8_t mask1;
+
+    /** Mask of the PIC2 */
+    uint8_t mask2;
+
+    /** Mode of PIC1. Not used for anything */
+    uint8_t mode1;
+
+    /** Mode of PIC2. Not used for anything */
+    uint8_t mode2;
+
+    /** Raw PIC interrupt register before masking */
+    uint8_t picr; //Raw PIC interrput register
+
+    /** Is the pic interrupting right now or not. */
+    bool picInterrupting;
+
+    /** A pointer to the Tsunami device which be belong to */
+    Tsunami *tsunami;
+
+    /** Intel 8253 Periodic Interval Timer */
+    PITimer pitimer;
+
+    RTC rtc;
+
+    /** The interval is set via two writes to the PIT.
+     * This variable contains a flag as to how many writes have happened, and
+     * the time so far.
+     */
+    uint16_t timerData;
+
+  public:
+    /**
+     * Return the freqency of the RTC
+     * @return interrupt rate of the RTC
+     */
+    Tick frequency() const;
+
+    struct Params : public BasicPioDevice::Params
+    {
+        Tick frequency;
+        Tsunami *tsunami;
+        time_t init_time;
+    };
+  protected:
+    const Params *params() const { return (const Params*)_params; }
+
+  public:
+    /**
+     * Initialize all the data for devices supported by Tsunami I/O.
+     * @param p pointer to Params struct
+     */
+    TsunamiIO(Params *p);
+
+    virtual Tick read(PacketPtr pkt);
+    virtual Tick write(PacketPtr pkt);
+
+    /**
+     * Post an PIC interrupt to the CPU via the CChip
+     * @param bitvector interrupt to post.
+     */
+    void postPIC(uint8_t bitvector);
+
+    /**
+     * Clear a posted interrupt
+     * @param bitvector interrupt to clear
+     */
+    void clearPIC(uint8_t bitvector);
+
+    /**
+     * Serialize this object to the given output stream.
+     * @param os The stream to serialize to.
+     */
+    virtual void serialize(std::ostream &os);
+
+    /**
+     * Reconstruct the state of this object from a checkpoint.
+     * @param cp The checkpoint use.
+     * @param section The section name of this object
+     */
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+};
+
+#endif // __DEV_TSUNAMI_IO_HH__
diff --git a/src/dev/alpha/tsunami_pchip.cc b/src/dev/alpha/tsunami_pchip.cc
new file mode 100644
index 000000000..94a7f96e5
--- /dev/null
+++ b/src/dev/alpha/tsunami_pchip.cc
@@ -0,0 +1,369 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Andrew Schultz
+ */
+
+/** @file
+ * Tsunami PChip (pci)
+ */
+
+#include <deque>
+#include <string>
+#include <vector>
+
+#include "base/trace.hh"
+#include "dev/alpha/tsunami_pchip.hh"
+#include "dev/alpha/tsunamireg.h"
+#include "dev/alpha/tsunami.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "sim/builder.hh"
+#include "sim/system.hh"
+
+using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
+
+TsunamiPChip::TsunamiPChip(Params *p)
+: BasicPioDevice(p)
+{
+    pioSize = 0xfff;
+
+    for (int i = 0; i < 4; i++) {
+        wsba[i] = 0;
+        wsm[i] = 0;
+        tba[i] = 0;
+    }
+
+    // initialize pchip control register
+    pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
+
+    //Set back pointer in tsunami
+    p->tsunami->pchip = this;
+}
+
+Tick
+TsunamiPChip::read(PacketPtr pkt)
+{
+    assert(pkt->result == Packet::Unknown);
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+
+    pkt->allocate();
+    Addr daddr = (pkt->getAddr() - pioAddr) >> 6;;
+    assert(pkt->getSize() == sizeof(uint64_t));
+
+
+    DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
+
+    switch(daddr) {
+      case TSDEV_PC_WSBA0:
+            pkt->set(wsba[0]);
+            break;
+      case TSDEV_PC_WSBA1:
+            pkt->set(wsba[1]);
+            break;
+      case TSDEV_PC_WSBA2:
+            pkt->set(wsba[2]);
+            break;
+      case TSDEV_PC_WSBA3:
+            pkt->set(wsba[3]);
+            break;
+      case TSDEV_PC_WSM0:
+            pkt->set(wsm[0]);
+            break;
+      case TSDEV_PC_WSM1:
+            pkt->set(wsm[1]);
+            break;
+      case TSDEV_PC_WSM2:
+            pkt->set(wsm[2]);
+            break;
+      case TSDEV_PC_WSM3:
+            pkt->set(wsm[3]);
+            break;
+      case TSDEV_PC_TBA0:
+            pkt->set(tba[0]);
+            break;
+      case TSDEV_PC_TBA1:
+            pkt->set(tba[1]);
+            break;
+      case TSDEV_PC_TBA2:
+            pkt->set(tba[2]);
+            break;
+      case TSDEV_PC_TBA3:
+            pkt->set(tba[3]);
+            break;
+      case TSDEV_PC_PCTL:
+            pkt->set(pctl);
+            break;
+      case TSDEV_PC_PLAT:
+            panic("PC_PLAT not implemented\n");
+      case TSDEV_PC_RES:
+            panic("PC_RES not implemented\n");
+      case TSDEV_PC_PERROR:
+            pkt->set((uint64_t)0x00);
+            break;
+      case TSDEV_PC_PERRMASK:
+            pkt->set((uint64_t)0x00);
+            break;
+      case TSDEV_PC_PERRSET:
+            panic("PC_PERRSET not implemented\n");
+      case TSDEV_PC_TLBIV:
+            panic("PC_TLBIV not implemented\n");
+      case TSDEV_PC_TLBIA:
+            pkt->set((uint64_t)0x00); // shouldn't be readable, but linux
+            break;
+      case TSDEV_PC_PMONCTL:
+            panic("PC_PMONCTL not implemented\n");
+      case TSDEV_PC_PMONCNT:
+            panic("PC_PMONCTN not implemented\n");
+      default:
+          panic("Default in PChip Read reached reading 0x%x\n", daddr);
+    }
+    pkt->result = Packet::Success;
+    return pioDelay;
+
+}
+
+Tick
+TsunamiPChip::write(PacketPtr pkt)
+{
+    assert(pkt->result == Packet::Unknown);
+    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+    Addr daddr = (pkt->getAddr() - pioAddr) >> 6;
+
+    assert(pkt->getSize() == sizeof(uint64_t));
+
+    DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
+
+    switch(daddr) {
+        case TSDEV_PC_WSBA0:
+              wsba[0] = pkt->get<uint64_t>();
+              break;
+        case TSDEV_PC_WSBA1:
+              wsba[1] = pkt->get<uint64_t>();
+              break;
+        case TSDEV_PC_WSBA2:
+              wsba[2] = pkt->get<uint64_t>();
+              break;
+        case TSDEV_PC_WSBA3:
+              wsba[3] = pkt->get<uint64_t>();
+              break;
+        case TSDEV_PC_WSM0:
+              wsm[0] = pkt->get<uint64_t>();
+              break;
+        case TSDEV_PC_WSM1:
+              wsm[1] = pkt->get<uint64_t>();
+              break;
+        case TSDEV_PC_WSM2:
+              wsm[2] = pkt->get<uint64_t>();
+              break;
+        case TSDEV_PC_WSM3:
+              wsm[3] = pkt->get<uint64_t>();
+              break;
+        case TSDEV_PC_TBA0:
+              tba[0] = pkt->get<uint64_t>();
+              break;
+        case TSDEV_PC_TBA1:
+              tba[1] = pkt->get<uint64_t>();
+              break;
+        case TSDEV_PC_TBA2:
+              tba[2] = pkt->get<uint64_t>();
+              break;
+        case TSDEV_PC_TBA3:
+              tba[3] = pkt->get<uint64_t>();
+              break;
+        case TSDEV_PC_PCTL:
+              pctl = pkt->get<uint64_t>();
+              break;
+        case TSDEV_PC_PLAT:
+              panic("PC_PLAT not implemented\n");
+        case TSDEV_PC_RES:
+              panic("PC_RES not implemented\n");
+        case TSDEV_PC_PERROR:
+              break;
+        case TSDEV_PC_PERRMASK:
+              panic("PC_PERRMASK not implemented\n");
+        case TSDEV_PC_PERRSET:
+              panic("PC_PERRSET not implemented\n");
+        case TSDEV_PC_TLBIV:
+              panic("PC_TLBIV not implemented\n");
+        case TSDEV_PC_TLBIA:
+              break; // value ignored, supposted to invalidate SG TLB
+        case TSDEV_PC_PMONCTL:
+              panic("PC_PMONCTL not implemented\n");
+        case TSDEV_PC_PMONCNT:
+              panic("PC_PMONCTN not implemented\n");
+        default:
+            panic("Default in PChip write reached reading 0x%x\n", daddr);
+
+    } // uint64_t
+
+    pkt->result = Packet::Success;
+    return pioDelay;
+}
+
+#define DMA_ADDR_MASK ULL(0x3ffffffff)
+
+Addr
+TsunamiPChip::translatePciToDma(Addr busAddr)
+{
+    // compare the address to the window base registers
+    uint64_t tbaMask = 0;
+    uint64_t baMask = 0;
+
+    uint64_t windowMask = 0;
+    uint64_t windowBase = 0;
+
+    uint64_t pteEntry = 0;
+
+    Addr pteAddr;
+    Addr dmaAddr;
+
+#if 0
+    DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr);
+    for (int i = 0; i < 4; i++) {
+        DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n",
+                i, wsba[i], wsm[i]);
+
+        windowBase = wsba[i];
+        windowMask = ~wsm[i] & (ULL(0xfff) << 20);
+
+        if ((busAddr & windowMask) == (windowBase & windowMask)) {
+            DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
+                    i, windowBase, windowMask, (busAddr & windowMask),
+                    (windowBase & windowMask));
+        }
+    }
+#endif
+
+    for (int i = 0; i < 4; i++) {
+
+        windowBase = wsba[i];
+        windowMask = ~wsm[i] & (ULL(0xfff) << 20);
+
+        if ((busAddr & windowMask) == (windowBase & windowMask)) {
+
+            if (wsba[i] & 0x1) {   // see if enabled
+                if (wsba[i] & 0x2) { // see if SG bit is set
+                    /** @todo
+                        This currently is faked by just doing a direct
+                        read from memory, however, to be realistic, this
+                        needs to actually do a bus transaction.  The process
+                        is explained in the tsunami documentation on page
+                        10-12 and basically munges the address to look up a
+                        PTE from a table in memory and then uses that mapping
+                        to create an address for the SG page
+                    */
+
+                    tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
+                    baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
+                    pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
+
+                    pioPort->readBlob(pteAddr, (uint8_t*)&pteEntry, sizeof(uint64_t));
+
+                    dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff));
+
+                } else {
+                    baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff);
+                    tbaMask = ~baMask;
+                    dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask);
+                }
+
+                return (dmaAddr & DMA_ADDR_MASK);
+            }
+        }
+    }
+
+    // if no match was found, then return the original address
+    return busAddr;
+}
+Addr
+TsunamiPChip::calcConfigAddr(int bus, int dev, int func)
+{
+    assert(func < 8);
+    assert(dev < 32);
+    assert(bus == 0);
+
+    return TsunamiPciBus0Config | (func << 8) | (dev << 11);
+}
+
+
+
+void
+TsunamiPChip::serialize(std::ostream &os)
+{
+    SERIALIZE_SCALAR(pctl);
+    SERIALIZE_ARRAY(wsba, 4);
+    SERIALIZE_ARRAY(wsm, 4);
+    SERIALIZE_ARRAY(tba, 4);
+}
+
+void
+TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
+{
+    UNSERIALIZE_SCALAR(pctl);
+    UNSERIALIZE_ARRAY(wsba, 4);
+    UNSERIALIZE_ARRAY(wsm, 4);
+    UNSERIALIZE_ARRAY(tba, 4);
+}
+
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
+
+    Param<Addr> pio_addr;
+    Param<Tick> pio_latency;
+    SimObjectParam<Platform *> platform;
+    SimObjectParam<System *> system;
+    SimObjectParam<Tsunami *> tsunami;
+
+END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
+
+    INIT_PARAM(pio_addr, "Device Address"),
+    INIT_PARAM(pio_latency, "Programmed IO latency"),
+    INIT_PARAM(platform, "platform"),
+    INIT_PARAM(system, "system object"),
+    INIT_PARAM(tsunami, "Tsunami")
+
+END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
+
+CREATE_SIM_OBJECT(TsunamiPChip)
+{
+    TsunamiPChip::Params *p = new TsunamiPChip::Params;
+    p->name = getInstanceName();
+    p->pio_addr = pio_addr;
+    p->pio_delay = pio_latency;
+    p->platform = platform;
+    p->system = system;
+    p->tsunami = tsunami;
+    return new TsunamiPChip(p);
+}
+
+REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
diff --git a/src/dev/alpha/tsunami_pchip.hh b/src/dev/alpha/tsunami_pchip.hh
new file mode 100644
index 000000000..1632a36d4
--- /dev/null
+++ b/src/dev/alpha/tsunami_pchip.hh
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * Tsunami PCI interface CSRs
+ */
+
+#ifndef __TSUNAMI_PCHIP_HH__
+#define __TSUNAMI_PCHIP_HH__
+
+#include "dev/alpha/tsunami.hh"
+#include "base/range.hh"
+#include "dev/io_device.hh"
+
+/**
+ * A very simple implementation of the Tsunami PCI interface chips.
+ */
+class TsunamiPChip : public BasicPioDevice
+{
+  protected:
+
+    static const Addr TsunamiPciBus0Config = ULL(0x801fe000000);
+
+    /** Pchip control register */
+    uint64_t pctl;
+
+    /** Window Base addresses */
+    uint64_t wsba[4];
+
+    /** Window masks */
+    uint64_t wsm[4];
+
+    /** Translated Base Addresses */
+    uint64_t tba[4];
+
+  public:
+    struct Params : public BasicPioDevice::Params
+    {
+        Tsunami *tsunami;
+    };
+  protected:
+    const Params *params() const { return (const Params*)_params; }
+
+  public:
+    /**
+     * Register the PChip with the mmu and init all wsba, wsm, and tba to 0
+     * @param p pointer to the parameters struct
+     */
+    TsunamiPChip(Params *p);
+
+    /**
+     * Translate a PCI bus address to a memory address for DMA.
+     * @todo Andrew says this needs to be fixed. What's wrong with it?
+     * @param busAddr PCI address to translate.
+     * @return memory system address
+     */
+    Addr translatePciToDma(Addr busAddr);
+
+    Addr calcConfigAddr(int bus, int dev, int func);
+
+    virtual Tick read(PacketPtr pkt);
+    virtual Tick write(PacketPtr pkt);
+
+    /**
+     * Serialize this object to the given output stream.
+     * @param os The stream to serialize to.
+     */
+    virtual void serialize(std::ostream &os);
+
+    /**
+     * Reconstruct the state of this object from a checkpoint.
+     * @param cp The checkpoint use.
+     * @param section The section name of this object
+     */
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+};
+
+#endif // __TSUNAMI_PCHIP_HH__
diff --git a/src/dev/alpha/tsunamireg.h b/src/dev/alpha/tsunamireg.h
new file mode 100644
index 000000000..d603972be
--- /dev/null
+++ b/src/dev/alpha/tsunamireg.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * List of Tsunami CSRs
+ */
+
+#ifndef __TSUNAMIREG_H__
+#define __TSUNAMIREG_H__
+
+#define ALPHA_K0SEG_BASE  ULL(0xfffffc0000000000)
+
+// CChip Registers
+#define TSDEV_CC_CSR    0x00
+#define TSDEV_CC_MTR    0x01
+#define TSDEV_CC_MISC   0x02
+
+#define TSDEV_CC_AAR0   0x04
+#define TSDEV_CC_AAR1   0x05
+#define TSDEV_CC_AAR2   0x06
+#define TSDEV_CC_AAR3   0x07
+#define TSDEV_CC_DIM0   0x08
+#define TSDEV_CC_DIM1   0x09
+#define TSDEV_CC_DIR0   0x0A
+#define TSDEV_CC_DIR1   0x0B
+#define TSDEV_CC_DRIR   0x0C
+#define TSDEV_CC_PRBEN  0x0D
+#define TSDEV_CC_IIC0   0x0E
+#define TSDEV_CC_IIC1   0x0F
+#define TSDEV_CC_MPR0   0x10
+#define TSDEV_CC_MPR1   0x11
+#define TSDEV_CC_MPR2   0x12
+#define TSDEV_CC_MPR3   0x13
+
+#define TSDEV_CC_DIM2   0x18
+#define TSDEV_CC_DIM3   0x19
+#define TSDEV_CC_DIR2   0x1A
+#define TSDEV_CC_DIR3   0x1B
+#define TSDEV_CC_IIC2   0x1C
+#define TSDEV_CC_IIC3   0x1D
+
+// BigTsunami Registers
+#define TSDEV_CC_BDIMS  0x1000000
+#define TSDEV_CC_BDIRS  0x2000000
+#define TSDEV_CC_IPIQ   0x20  //0xf01a000800
+#define TSDEV_CC_IPIR   0x21  //0xf01a000840
+#define TSDEV_CC_ITIR   0x22  //0xf01a000880
+
+
+// PChip Registers
+#define TSDEV_PC_WSBA0      0x00
+#define TSDEV_PC_WSBA1      0x01
+#define TSDEV_PC_WSBA2      0x02
+#define TSDEV_PC_WSBA3      0x03
+#define TSDEV_PC_WSM0       0x04
+#define TSDEV_PC_WSM1       0x05
+#define TSDEV_PC_WSM2       0x06
+#define TSDEV_PC_WSM3       0x07
+#define TSDEV_PC_TBA0       0x08
+#define TSDEV_PC_TBA1       0x09
+#define TSDEV_PC_TBA2       0x0A
+#define TSDEV_PC_TBA3       0x0B
+#define TSDEV_PC_PCTL       0x0C
+#define TSDEV_PC_PLAT       0x0D
+#define TSDEV_PC_RES        0x0E
+#define TSDEV_PC_PERROR     0x0F
+#define TSDEV_PC_PERRMASK   0x10
+#define TSDEV_PC_PERRSET    0x11
+#define TSDEV_PC_TLBIV      0x12
+#define TSDEV_PC_TLBIA      0x13
+#define TSDEV_PC_PMONCTL    0x14
+#define TSDEV_PC_PMONCNT    0x15
+
+#define TSDEV_PC_SPST       0x20
+
+
+// DChip Registers
+#define TSDEV_DC_DSC        0x20
+#define TSDEV_DC_STR        0x21
+#define TSDEV_DC_DREV       0x22
+#define TSDEV_DC_DSC2       0x23
+
+// I/O Ports
+#define TSDEV_PIC1_MASK     0x21
+#define TSDEV_PIC2_MASK     0xA1
+#define TSDEV_PIC1_ISR      0x20
+#define TSDEV_PIC2_ISR      0xA0
+#define TSDEV_PIC1_ACK      0x20
+#define TSDEV_PIC2_ACK      0xA0
+#define TSDEV_DMA1_RESET    0x0D
+#define TSDEV_DMA2_RESET    0xDA
+#define TSDEV_DMA1_MODE     0x0B
+#define TSDEV_DMA2_MODE     0xD6
+#define TSDEV_DMA1_MASK     0x0A
+#define TSDEV_DMA2_MASK     0xD4
+#define TSDEV_CTRL_PORTB    0x61
+#define TSDEV_TMR0_DATA     0x40
+#define TSDEV_TMR1_DATA     0x41
+#define TSDEV_TMR2_DATA     0x42
+#define TSDEV_TMR_CTRL      0x43
+#define TSDEV_KBD           0x64
+#define TSDEV_DMA1_CMND     0x08
+#define TSDEV_DMA1_STAT     TSDEV_DMA1_CMND
+#define TSDEV_DMA2_CMND     0xD0
+#define TSDEV_DMA2_STAT     TSDEV_DMA2_CMND
+#define TSDEV_DMA1_MMASK    0x0F
+#define TSDEV_DMA2_MMASK    0xDE
+
+/* Added for keyboard accesses */
+#define TSDEV_KBD           0x64
+
+/* Added for ATA PCI DMA */
+#define ATA_PCI_DMA         0x00
+#define ATA_PCI_DMA2        0x02
+#define ATA_PCI_DMA3        0x16
+#define ATA_PCI_DMA4        0x17
+#define ATA_PCI_DMA5        0x1a
+#define ATA_PCI_DMA6        0x11
+#define ATA_PCI_DMA7        0x14
+
+#define TSDEV_RTC_ADDR      0x70
+#define TSDEV_RTC_DATA      0x71
+
+#define PCHIP_PCI0_MEMORY       ULL(0x00000000000)
+#define PCHIP_PCI0_IO           ULL(0x001FC000000)
+#define TSUNAMI_UNCACHABLE_BIT  ULL(0x80000000000)
+#define TSUNAMI_PCI0_MEMORY     TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY
+#define TSUNAMI_PCI0_IO         TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO
+
+
+// UART Defines
+#define UART_IER_RDI            0x01
+#define UART_IER_THRI           0x02
+#define UART_IER_RLSI           0x04
+
+
+#define UART_LSR_TEMT   0x40
+#define UART_LSR_THRE   0x20
+#define UART_LSR_DR     0x01
+
+#define UART_MCR_LOOP   0x10
+
+// System Control PortB Status Bits
+#define PORTB_SPKR_HIGH 0x20
+
+#endif // __TSUNAMIREG_H__