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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-12-21 10:26:55 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-04 13:24:40 +0000 |
| commit | 90ed58bcb1791b36e2ecc585ff91b842b1d89610 (patch) | |
| tree | 510f5bf72b23269c1308c5765ee7f1d4d8302f24 /src/dev/arm/Gic.py | |
| parent | 75831ce5b7880b67c1aa2e0871ce16d5c01cadc7 (diff) | |
| download | gem5-90ed58bcb1791b36e2ecc585ff91b842b1d89610.tar.xz | |
dev-arm: Implement GIC-400 model from GicV2
Implementation registers for the GICv2 model currently hold values
referring to a GIC-400 implementation. This patch is making them
parametrizable so that it is possible to instantiate a GIC-400 model.
The patch is also modifying Realview platform to use new GIC-400 model
in lieau of GICv2.
Change-Id: I446db8c796ee3c2708af91e9139f0a6e7947321b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15277
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev/arm/Gic.py')
| -rw-r--r-- | src/dev/arm/Gic.py | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py index 622dcf616..dddb7dfac 100644 --- a/src/dev/arm/Gic.py +++ b/src/dev/arm/Gic.py @@ -49,6 +49,15 @@ class BaseGic(PioDevice): platform = Param.Platform(Parent.any, "Platform this device is part of.") + gicd_iidr = Param.UInt32(0, + "Distributor Implementer Identification Register") + gicd_pidr = Param.UInt32(0, + "Peripheral Identification Register") + gicc_iidr = Param.UInt32(0, + "CPU Interface Identification Register") + gicv_iidr = Param.UInt32(0, + "VM CPU Interface Identification Register") + class ArmInterruptPin(SimObject): type = 'ArmInterruptPin' cxx_header = "dev/arm/base_gic.hh" @@ -81,6 +90,19 @@ class GicV2(BaseGic): it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)") gem5_extensions = Param.Bool(False, "Enable gem5 extensions") +class Gic400(GicV2): + """ + As defined in: + "ARM Generic Interrupt Controller Architecture" version 2.0 + "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1 + """ + gicd_pidr = 0x002bb490 + gicd_iidr = 0x0200143B + gicc_iidr = 0x0202143B + + # gicv_iidr same as gicc_idr + gicv_iidr = gicc_iidr + class Gicv2mFrame(SimObject): type = 'Gicv2mFrame' cxx_header = "dev/arm/gic_v2m.hh" @@ -107,6 +129,10 @@ class VGic(PioDevice): # The number of list registers is not currently configurable at runtime. ppint = Param.UInt32("HV maintenance interrupt number") + # gicv_iidr same as gicc_idr + gicv_iidr = Param.UInt32(Self.gic.gicc_iidr, + "VM CPU Interface Identification Register") + def generateDeviceTree(self, state): gic = self.gic.unproxy(self) |