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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:33 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:33 -0400 |
| commit | 49d88f08b0ff463bca04285dca240b3730889a1d (patch) | |
| tree | e4affba86713db0136091f1c9c25ff6e975048a9 /src/dev/arm/RealView.py | |
| parent | e553844efc4247f5be870fad5ea919af85858a55 (diff) | |
| download | gem5-49d88f08b0ff463bca04285dca240b3730889a1d.tar.xz | |
mem: Change AbstractMemory defaults to match the common case
This patch changes the default parameter value of conf_table_reported
to match the common case. It also simplifies the regression and config
scripts to reflect this change.
Diffstat (limited to 'src/dev/arm/RealView.py')
| -rw-r--r-- | src/dev/arm/RealView.py | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index 731e8abe7..167108850 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -159,8 +159,8 @@ class RealView(Platform): max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") def setupBootLoader(self, mem_bus, cur_sys, loc): - self.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'), - size = '64MB')) + self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), + conf_table_reported = False) self.nvmem.port = mem_bus.master cur_sys.boot_loader = loc('boot.arm') @@ -357,7 +357,8 @@ class VExpress_EMM(RealView): InterruptLine=2, InterruptPin=2) - vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB')) + vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), + conf_table_reported = False) rtc = PL031(pio_addr=0x1C170000, int_num=36) l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) @@ -372,7 +373,8 @@ class VExpress_EMM(RealView): mmc_fake = AmbaFake(pio_addr=0x1c050000) def setupBootLoader(self, mem_bus, cur_sys, loc): - self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) + self.nvmem = SimpleMemory(range = AddrRange('64MB'), + conf_table_reported = False) self.nvmem.port = mem_bus.master cur_sys.boot_loader = loc('boot_emm.arm') cur_sys.atags_addr = 0x80000100 |