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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2015-04-08 15:56:06 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2015-04-08 15:56:06 -0500 |
| commit | c3268f882029c7501867540ccf04db054fdff084 (patch) | |
| tree | 6c31899946f53d46a0b7bbbfe7fd5dc782dfde2c /src/dev/arm/RealView.py | |
| parent | f05cb84ed1a61f81c26e4ea22f98454d12f069aa (diff) | |
| download | gem5-c3268f882029c7501867540ccf04db054fdff084.tar.xz | |
config: Support full-system with SST's memory system
This patch adds an example configuration in ext/sst/tests/ that allows
an SST/gem5 instance to simulate a 4-core AArch64 system with SST's
memHierarchy components providing all the caches and memories.
Diffstat (limited to 'src/dev/arm/RealView.py')
| -rw-r--r-- | src/dev/arm/RealView.py | 33 |
1 files changed, 17 insertions, 16 deletions
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index 9c9eff710..95edb9d53 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -1,4 +1,4 @@ -# Copyright (c) 2009-2014 ARM Limited +# Copyright (c) 2009-2015 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -509,21 +509,22 @@ class VExpress_EMM(RealView): # Attach I/O devices that are on chip and also set the appropriate # ranges for the bridge - def attachOnChipIO(self, bus, bridge): - self.gic.pio = bus.master - self.local_cpu_timer.pio = bus.master - if hasattr(self, "gicv2m"): - self.gicv2m.pio = bus.master - self.hdlcd.dma = bus.slave - # Bridge ranges based on excluding what is part of on-chip I/O - # (gic, a9scu) - bridge.ranges = [AddrRange(0x2F000000, size='16MB'), - AddrRange(0x2B000000, size='4MB'), - AddrRange(0x30000000, size='256MB'), - AddrRange(0x40000000, size='512MB'), - AddrRange(0x18000000, size='64MB'), - AddrRange(0x1C000000, size='64MB')] - self.vgic.pio = bus.master + def attachOnChipIO(self, bus, bridge=None): + self.gic.pio = bus.master + self.vgic.pio = bus.master + self.local_cpu_timer.pio = bus.master + if hasattr(self, "gicv2m"): + self.gicv2m.pio = bus.master + self.hdlcd.dma = bus.slave + if bridge: + # Bridge ranges based on excluding what is part of on-chip I/O + # (gic, a9scu) + bridge.ranges = [AddrRange(0x2F000000, size='16MB'), + AddrRange(0x2B000000, size='4MB'), + AddrRange(0x30000000, size='256MB'), + AddrRange(0x40000000, size='512MB'), + AddrRange(0x18000000, size='64MB'), + AddrRange(0x1C000000, size='64MB')] # Set the clock domain for IO objects that are considered |