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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-04-16 09:20:22 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-05-22 15:17:15 +0000 |
| commit | 5830ee78b6dcab87cf383a6cab1e534e1ae1baae (patch) | |
| tree | f6a3cce02b1ff377695fba195f8092877f0c4ed3 /src/dev/arm/RealView.py | |
| parent | dd8a7694806e3f816ba688d2094106db68b46b53 (diff) | |
| download | gem5-5830ee78b6dcab87cf383a6cab1e534e1ae1baae.tar.xz | |
dev-arm: Provide a GICv3 ITS Implementation
This patch introduces the GICv3 ITS module, which is in charge of
translating MSIs into physical (GICv3) and virtual (GICv4) LPIs. The
patch is only GICv3 compliant, which means that there is no direct
virtual LPI injection (this also means V* commands are unimplemented)
Other missing features are:
* No 2level ITS tables (only flat table supported)
* Command errors: when there is an error in the ITS, it is
IMPLEMENTATION DEFINED on how the ITS behaves. There are three possible
scenarios (see GICv3 TRM) and this implementation only supports one of
these (which is, aborting the command and jumping to the next one).
Furter patches could make it possible to select different reactions
* Invalidation commands (INV, INVALL) are only doing the memory table
walks, assuming the current Gicv3Redistributor is not caching any
configuration table entry.
Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/dev/arm/RealView.py')
| -rw-r--r-- | src/dev/arm/RealView.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index 186d6df41..b34ab006c 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -1084,14 +1084,15 @@ class VExpress_GEM5_V1(VExpress_GEM5_V1_Base): class VExpress_GEM5_V2_Base(VExpress_GEM5_Base): gic = Gicv3(dist_addr=0x2c000000, redist_addr=0x2c010000, - maint_int=ArmPPI(num=25)) + maint_int=ArmPPI(num=25), + its=Gicv3Its(pio_addr=0x2c120000)) # Limiting to 128 since it will otherwise overlap with PCI space gic.cpu_max = 128 def _on_chip_devices(self): return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [ - self.gic, + self.gic, self.gic.its ] def setupBootLoader(self, mem_bus, cur_sys, loc): |