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| author | Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com> | 2010-10-01 16:04:00 -0500 |
|---|---|---|
| committer | Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com> | 2010-10-01 16:04:00 -0500 |
| commit | 9792bbc32400f522830ff8d92209c672d12440f3 (patch) | |
| tree | 3ff0914c7f9fbde791317460bb48fa33c920d104 /src/dev/arm/SConscript | |
| parent | 521d68c82a2399bfe32f282aa58708103369b99c (diff) | |
| download | gem5-9792bbc32400f522830ff8d92209c672d12440f3.tar.xz | |
ARM: Fix some subtle bugs in the GIC
The GIC code can write to the registers with 8, 16, or 32 byte
accesses which could set/clear different numbers of interrupts.
Diffstat (limited to 'src/dev/arm/SConscript')
| -rw-r--r-- | src/dev/arm/SConscript | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript index 423bf1726..66a97a92e 100644 --- a/src/dev/arm/SConscript +++ b/src/dev/arm/SConscript @@ -51,3 +51,4 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'arm': Source('realview.cc') TraceFlag('AMBA') + TraceFlag('GIC') |