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| author | Adrian Herrera <adrian.herrera@arm.com> | 2019-10-24 12:47:22 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2020-01-22 11:37:13 +0000 |
| commit | 2f2f508c74b532ef4b9e083879a6c27b17e7bcb1 (patch) | |
| tree | 98303e27b3a51beef30dd3cabd97cf29fc2aecf2 /src/dev/arm/SConscript | |
| parent | c145876cef258637ec30996d3f3c73e33fd58a4a (diff) | |
| download | gem5-2f2f508c74b532ef4b9e083879a6c27b17e7bcb1.tar.xz | |
dev-arm: add Watchdog Module SP805 model
This provides a model of the Arm Watchdog Module SP805. This is based
on the public TRM rev. r1p0 (ARM DDI 0270B). Integration test harness
is not supported. Auto-generation of device tree entries is provided.
Change-Id: I6157cec2212d0a1d2685bcfa983d2acbae1f3377
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24205
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/dev/arm/SConscript')
| -rw-r--r-- | src/dev/arm/SConscript | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript index c2df3ef51..66a368df0 100644 --- a/src/dev/arm/SConscript +++ b/src/dev/arm/SConscript @@ -81,6 +81,7 @@ if env['TARGET_ISA'] == 'arm': Source('smmu_v3_slaveifc.cc'); Source('smmu_v3_transl.cc'); Source('timer_sp804.cc') + Source('watchdog_sp805.cc') Source('gpu_nomali.cc') Source('pci_host.cc') Source('rv_ctrl.cc') @@ -104,6 +105,7 @@ if env['TARGET_ISA'] == 'arm': DebugFlag('RVCTRL') DebugFlag('SMMUv3') DebugFlag('SMMUv3Hazard') + DebugFlag('Sp805') DebugFlag('EnergyCtrl') DebugFlag('UFSHostDevice') DebugFlag('VGIC') |