diff options
author | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-03-23 18:49:57 +0000 |
---|---|---|
committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-06-07 12:36:44 +0000 |
commit | 409fbc653f5177f9f1da91877591a27b27302a3b (patch) | |
tree | 654a2b987fb207ea16e18254020d01ba4386c150 /src/dev/arm/base_gic.hh | |
parent | 60600f09c25255b3c8f72da7fb49100e2682093a (diff) | |
download | gem5-409fbc653f5177f9f1da91877591a27b27302a3b.tar.xz |
dev-arm: Add a GIC interrupt adaptor
Add GIC-based interrupt adaptor implementations that support PPI
(ArmPPI) and SPI (ArmSPI) delivery. In addition to being useful for
"normal" memory-mapped devices, the PPI adaptor makes it possible to
use the same device model to generate both PPIs and SPIs (e.g., the
PMU).
Change-Id: I73d6591c168040faef2443430c4f1da10c387a2a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2521
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/dev/arm/base_gic.hh')
-rw-r--r-- | src/dev/arm/base_gic.hh | 74 |
1 files changed, 72 insertions, 2 deletions
diff --git a/src/dev/arm/base_gic.hh b/src/dev/arm/base_gic.hh index cd16c0362..73d73e471 100644 --- a/src/dev/arm/base_gic.hh +++ b/src/dev/arm/base_gic.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013, 2017 ARM Limited + * Copyright (c) 2012-2013, 2017-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -47,11 +47,18 @@ #include "dev/io_device.hh" class Platform; +class RealView; +class ThreadContext; + +struct ArmInterruptPinParams; +struct ArmPPIParams; +struct ArmSPIParams; +struct BaseGicParams; class BaseGic : public PioDevice { public: - typedef struct BaseGicParams Params; + typedef BaseGicParams Params; BaseGic(const Params *p); virtual ~BaseGic(); @@ -103,4 +110,67 @@ class BaseGicRegisters virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0; }; +/** + * Generic representation of an Arm interrupt pin. + */ +class ArmInterruptPin : public SimObject +{ + public: + ArmInterruptPin(const ArmInterruptPinParams *p); + + public: /* Public interface */ + /** + * Set the thread context owning this interrupt. + * + * This method is used to set the thread context for interrupts + * that are thread/CPU-specific. Only devices that are used in + * such a context are expected to call this method. + */ + void setThreadContext(ThreadContext *tc); + + /** Signal an interrupt */ + virtual void raise() = 0; + /** Clear a signalled interrupt */ + virtual void clear() = 0; + + protected: + /** + * Get the target context ID of this interrupt. + * + * @pre setThreadContext() must have been called prior to calling + * this method. + */ + ContextID targetContext() const; + + /** + * Pointer to the thread context that owns this interrupt in case + * it is a thread-/CPU-private interrupt + */ + const ThreadContext *threadContext; + + /** Arm platform to use for interrupt generation */ + RealView *const platform; + /** Interrupt number to generate */ + const uint32_t intNum; +}; + +class ArmSPI : public ArmInterruptPin +{ + public: + ArmSPI(const ArmSPIParams *p); + + void raise() override; + void clear() override; +}; + +class ArmPPI : public ArmInterruptPin +{ + public: + ArmPPI(const ArmPPIParams *p); + + void raise() override; + void clear() override; +}; + + #endif |