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| author | Matt Evans <matt.evans@arm.com> | 2013-10-17 10:20:45 -0500 |
|---|---|---|
| committer | Matt Evans <matt.evans@arm.com> | 2013-10-17 10:20:45 -0500 |
| commit | 94d17a547cc11b017f292f6b22cfd5169e1eef86 (patch) | |
| tree | 2f0a103623d5eb3a8f7b5c08d7cf048168481a99 /src/dev/arm/base_gic.hh | |
| parent | 2b9138135ee5c751136bb53738a44211557961f9 (diff) | |
| download | gem5-94d17a547cc11b017f292f6b22cfd5169e1eef86.tar.xz | |
arm: Add a 'clear PPI' method to gic_pl390
The underlying assumption that all PPIs must be edge-triggered is
strained when the architected timers and VGIC interfaces make
level-behaviour observable. For example, a virtual timer interrupt
'goes away' when the hypervisor is entered and the vtimer is disabled;
this requires a PPI to be de-activated.
The new method simply clears the interrupt pending state.
Diffstat (limited to 'src/dev/arm/base_gic.hh')
| -rw-r--r-- | src/dev/arm/base_gic.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/dev/arm/base_gic.hh b/src/dev/arm/base_gic.hh index d177487ed..facc99084 100644 --- a/src/dev/arm/base_gic.hh +++ b/src/dev/arm/base_gic.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 ARM Limited + * Copyright (c) 2012-2013 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -75,6 +75,7 @@ class BaseGic : public PioDevice * @param cpu CPU to forward interrupt to */ virtual void sendPPInt(uint32_t num, uint32_t cpu) = 0; + virtual void clearPPInt(uint32_t num, uint32_t cpu) = 0; /** * Clear an interrupt from a device that is connected to the GIC. |