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authorAndreas Sandberg <andreas.sandberg@arm.com>2018-03-22 17:58:59 +0000
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-09-10 09:57:26 +0000
commit476fd104a80095207eec0b594baa642937fbac01 (patch)
tree0ae88ae7223a5532a6e8191cb8aa3a25506db2c3 /src/dev/arm/generic_timer.cc
parenta3e0eb0b24c0c7145bbf8a247178323f58760ad5 (diff)
downloadgem5-476fd104a80095207eec0b594baa642937fbac01.tar.xz
dev, arm: Add misc reg tracing to the generic timer
Change-Id: Ice9376b8eb42423679b0191910e8c980f8017f88 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12398
Diffstat (limited to 'src/dev/arm/generic_timer.cc')
-rw-r--r--src/dev/arm/generic_timer.cc16
1 files changed, 15 insertions, 1 deletions
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 1d5e8bb00..260461e33 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013, 2015, 2017 ARM Limited
+ * Copyright (c) 2013, 2015, 2017-2018 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -521,6 +521,20 @@ GenericTimer::readMiscReg(int reg, unsigned cpu)
}
+void
+GenericTimerISA::setMiscReg(int reg, MiscReg val)
+{
+ DPRINTF(Timer, "Setting %s := 0x%x\n", miscRegName[reg], val);
+ parent.setMiscReg(reg, cpu, val);
+}
+
+MiscReg
+GenericTimerISA::readMiscReg(int reg)
+{
+ MiscReg value = parent.readMiscReg(reg, cpu);
+ DPRINTF(Timer, "Reading %s as 0x%x\n", miscRegName[reg], value);
+ return value;
+}
GenericTimerMem::GenericTimerMem(GenericTimerMemParams *p)
: PioDevice(p),