diff options
| author | Matt Evans <matt.evans@arm.com> | 2013-10-17 10:20:45 -0500 |
|---|---|---|
| committer | Matt Evans <matt.evans@arm.com> | 2013-10-17 10:20:45 -0500 |
| commit | 94d17a547cc11b017f292f6b22cfd5169e1eef86 (patch) | |
| tree | 2f0a103623d5eb3a8f7b5c08d7cf048168481a99 /src/dev/arm/gic_pl390.hh | |
| parent | 2b9138135ee5c751136bb53738a44211557961f9 (diff) | |
| download | gem5-94d17a547cc11b017f292f6b22cfd5169e1eef86.tar.xz | |
arm: Add a 'clear PPI' method to gic_pl390
The underlying assumption that all PPIs must be edge-triggered is
strained when the architected timers and VGIC interfaces make
level-behaviour observable. For example, a virtual timer interrupt
'goes away' when the hypervisor is entered and the vtimer is disabled;
this requires a PPI to be de-activated.
The new method simply clears the interrupt pending state.
Diffstat (limited to 'src/dev/arm/gic_pl390.hh')
| -rw-r--r-- | src/dev/arm/gic_pl390.hh | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh index c2b0988f8..2621e1a27 100644 --- a/src/dev/arm/gic_pl390.hh +++ b/src/dev/arm/gic_pl390.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010, 2013 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -287,6 +287,9 @@ class Pl390 : public BaseGic * Depending on the configuration, the gic may de-assert it's cpu line * @param number number of interrupt to send */ void clearInt(uint32_t number); + + /** Clear a (level-sensitive) PPI */ + void clearPPInt(uint32_t num, uint32_t cpu); /** @} */ /** @{ */ |