dev-arm: Create postFiq events for GICv2

GICv2 is signaling IRQs only to the CPU. This patch is adding the
capability of scheduling FIQs.

Change-Id: I395afc83eb8d58cfd32cd93372bcb6f804364ef5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12947
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 25 insertions, 1 deletions

diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 01358b732..7bbc89e74 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -88,6 +88,9 @@ GicV2::GicV2(const Params *p)
         postIntEvent[x] =
             new EventFunctionWrapper([this, x]{ postDelayedInt(x); },
                                      "Post Interrupt to CPU");
+        postFiqEvent[x] =
+            new EventFunctionWrapper([this, x]{ postDelayedFiq(x); },
+                                     "Post FIQ to CPU");
     }
     DPRINTF(Interrupt, "cpuEnabled[0]=%d cpuEnabled[1]=%d\n", cpuEnabled(0),
             cpuEnabled(1));
@@ -97,8 +100,10 @@ GicV2::GicV2(const Params *p)
 
 GicV2::~GicV2()
 {
-    for (int x = 0; x < CPU_MAX; x++)
+    for (int x = 0; x < CPU_MAX; x++) {
         delete postIntEvent[x];
+        delete postFiqEvent[x];
+    }
 }
 
 Tick
@@ -915,6 +920,25 @@ GicV2::postDelayedInt(uint32_t cpu)
         signalDrainDone();
 }
 
+void
+GicV2::postFiq(uint32_t cpu, Tick when)
+{
+    if (!(postFiqEvent[cpu]->scheduled())) {
+        ++pendingDelayedInterrupts;
+        eventq->schedule(postFiqEvent[cpu], when);
+    }
+}
+
+void
+GicV2::postDelayedFiq(uint32_t cpu)
+{
+    platform->intrctrl->post(cpu, ArmISA::INT_FIQ, 0);
+    --pendingDelayedInterrupts;
+    assert(pendingDelayedInterrupts >= 0);
+    if (pendingDelayedInterrupts == 0)
+        signalDrainDone();
+}
+
 DrainState
 GicV2::drain()
 {