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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-12-21 10:26:55 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-04 13:24:40 +0000 |
| commit | 90ed58bcb1791b36e2ecc585ff91b842b1d89610 (patch) | |
| tree | 510f5bf72b23269c1308c5765ee7f1d4d8302f24 /src/dev/arm/gic_v2.cc | |
| parent | 75831ce5b7880b67c1aa2e0871ce16d5c01cadc7 (diff) | |
| download | gem5-90ed58bcb1791b36e2ecc585ff91b842b1d89610.tar.xz | |
dev-arm: Implement GIC-400 model from GicV2
Implementation registers for the GICv2 model currently hold values
referring to a GIC-400 implementation. This patch is making them
parametrizable so that it is possible to instantiate a GIC-400 model.
The patch is also modifying Realview platform to use new GIC-400 model
in lieau of GICv2.
Change-Id: I446db8c796ee3c2708af91e9139f0a6e7947321b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15277
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev/arm/gic_v2.cc')
| -rw-r--r-- | src/dev/arm/gic_v2.cc | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc index 1e58718f9..fa480a222 100644 --- a/src/dev/arm/gic_v2.cc +++ b/src/dev/arm/gic_v2.cc @@ -64,6 +64,9 @@ const AddrRange GicV2::GICD_ICFGR (0xc00, 0xcff); GicV2::GicV2(const Params *p) : BaseGic(p), + gicdPIDR(p->gicd_pidr), + gicdIIDR(p->gicd_iidr), + giccIIDR(p->gicc_iidr), distRange(RangeSize(p->dist_addr, DIST_SIZE)), cpuRange(RangeSize(p->cpu_addr, p->cpu_size)), addrRanges{distRange, cpuRange}, @@ -268,16 +271,16 @@ GicV2::readDistributor(ContextID ctx, Addr daddr, size_t resp_sz) (haveGem5Extensions ? 0x100 : 0x0)); case GICD_PIDR0: //ARM defined DevID - return (GICD_400_PIDR_VALUE & 0xFF); + return (gicdPIDR & 0xFF); case GICD_PIDR1: - return ((GICD_400_PIDR_VALUE >> 8) & 0xFF); + return ((gicdPIDR >> 8) & 0xFF); case GICD_PIDR2: - return ((GICD_400_PIDR_VALUE >> 16) & 0xFF); + return ((gicdPIDR >> 16) & 0xFF); case GICD_PIDR3: - return ((GICD_400_PIDR_VALUE >> 24) & 0xFF); + return ((gicdPIDR >> 24) & 0xFF); case GICD_IIDR: /* revision id is resorted to 1 and variant to 0*/ - return GICD_400_IIDR_VALUE; + return gicdIIDR; default: panic("Tried to read Gic distributor at offset %#x\n", daddr); break; @@ -307,7 +310,7 @@ GicV2::readCpu(ContextID ctx, Addr daddr) { switch(daddr) { case GICC_IIDR: - return GICC_400_IIDR_VALUE; + return giccIIDR; case GICC_CTLR: return cpuControl[ctx]; case GICC_PMR: |