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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-11 13:15:18 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-01 08:28:51 +0000 |
| commit | 8b3c5309dff79402f7f96660a6d19e450a45356b (patch) | |
| tree | 2358964520867017a7da5cf7e011cbbf795b749e /src/dev/arm/gic_v2.cc | |
| parent | ef984784289f8bd4ddedcc4a6ead2c45704cc35b (diff) | |
| download | gem5-8b3c5309dff79402f7f96660a6d19e450a45356b.tar.xz | |
dev-arm: Implement GICv2 GICD_IGROUPR register
This patch is implementing GICD_IGROUPR register.
Change-Id: I1626f61fbf7deec9c81d8d2c135f1d6c0c4eb891
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12946
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev/arm/gic_v2.cc')
| -rw-r--r-- | src/dev/arm/gic_v2.cc | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc index 92949a34f..01358b732 100644 --- a/src/dev/arm/gic_v2.cc +++ b/src/dev/arm/gic_v2.cc @@ -161,7 +161,9 @@ uint32_t GicV2::readDistributor(ContextID ctx, Addr daddr, size_t resp_sz) { if (GICD_IGROUPR.contains(daddr)) { - return 0; // unimplemented; RAZ (read as zero) + uint32_t ix = (daddr - GICD_IGROUPR.start()) >> 2; + assert(ix < 32); + return getIntGroup(ctx, ix); } if (GICD_ISENABLER.contains(daddr)) { @@ -415,7 +417,10 @@ GicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data, size_t data_sz) { if (GICD_IGROUPR.contains(daddr)) { - return; // unimplemented; WI (writes ignored) + uint32_t ix = (daddr - GICD_IGROUPR.start()) >> 2; + assert(ix < 32); + getIntGroup(ctx, ix) |= data; + return; } if (GICD_ISENABLER.contains(daddr)) { @@ -938,6 +943,7 @@ GicV2::serialize(CheckpointOut &cp) const SERIALIZE_ARRAY(intEnabled, INT_BITS_MAX-1); SERIALIZE_ARRAY(pendingInt, INT_BITS_MAX-1); SERIALIZE_ARRAY(activeInt, INT_BITS_MAX-1); + SERIALIZE_ARRAY(intGroup, INT_BITS_MAX-1); SERIALIZE_ARRAY(iccrpr, CPU_MAX); SERIALIZE_ARRAY(intPriority, GLOBAL_INT_LINES); SERIALIZE_ARRAY(cpuTarget, GLOBAL_INT_LINES); @@ -967,6 +973,7 @@ GicV2::BankedRegs::serialize(CheckpointOut &cp) const SERIALIZE_SCALAR(intEnabled); SERIALIZE_SCALAR(pendingInt); SERIALIZE_SCALAR(activeInt); + SERIALIZE_SCALAR(intGroup); SERIALIZE_ARRAY(intPriority, SGI_MAX + PPI_MAX); } @@ -980,6 +987,7 @@ GicV2::unserialize(CheckpointIn &cp) UNSERIALIZE_ARRAY(intEnabled, INT_BITS_MAX-1); UNSERIALIZE_ARRAY(pendingInt, INT_BITS_MAX-1); UNSERIALIZE_ARRAY(activeInt, INT_BITS_MAX-1); + UNSERIALIZE_ARRAY(intGroup, INT_BITS_MAX-1); UNSERIALIZE_ARRAY(iccrpr, CPU_MAX); UNSERIALIZE_ARRAY(intPriority, GLOBAL_INT_LINES); UNSERIALIZE_ARRAY(cpuTarget, GLOBAL_INT_LINES); @@ -1024,6 +1032,7 @@ GicV2::BankedRegs::unserialize(CheckpointIn &cp) UNSERIALIZE_SCALAR(intEnabled); UNSERIALIZE_SCALAR(pendingInt); UNSERIALIZE_SCALAR(activeInt); + UNSERIALIZE_SCALAR(intGroup); UNSERIALIZE_ARRAY(intPriority, SGI_MAX + PPI_MAX); } |