dev-arm: Add basic support for level sensitive SPIs in GICv2

For level sensitive interrupt IRQ line must be cleared when interrupt is
deasserted. This is not the case for edge-trigerred interrupt.

Change-Id: Ib1660da74a296750c0eb9e20878d4ee64bd23130
Reviewed-on: https://gem5-review.googlesource.com/12944
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 18 insertions, 0 deletions

diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 5791250d1..352b108d0 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -262,6 +262,16 @@ class GicV2 : public BaseGic, public BaseGicRegisters
         }
     }
 
+    /** GICD_ICFGRn
+     * get 2 bit config associated to an interrupt.
+     */
+    uint8_t getIntConfig(ContextID ctx, uint32_t ix) {
+        assert(ix < INT_LINES_MAX);
+        const uint8_t cfg_low = intNumToBit(ix * 2);
+        const uint8_t cfg_hi = cfg_low + 1;
+        return bits(intConfig[intNumToWord(ix * 2)], cfg_hi, cfg_low);
+    }
+
     /** GICD_ITARGETSR{8..255}
      * an 8 bit cpu target id for each global interrupt.
      */
@@ -291,6 +301,14 @@ class GicV2 : public BaseGic, public BaseGicRegisters
      * and if it is 1:N or N:N */
     uint32_t intConfig[INT_BITS_MAX*2];
 
+    bool isLevelSensitive(ContextID ctx, uint32_t ix) {
+        if (ix == SPURIOUS_INT) {
+            return false;
+        } else {
+            return bits(getIntConfig(ctx, ix), 1) == 0;
+        }
+    }
+
     /** CPU enabled */
     bool cpuEnabled[CPU_MAX];