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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-12-21 10:26:55 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-04 13:24:40 +0000 |
| commit | 90ed58bcb1791b36e2ecc585ff91b842b1d89610 (patch) | |
| tree | 510f5bf72b23269c1308c5765ee7f1d4d8302f24 /src/dev/arm/gic_v2.hh | |
| parent | 75831ce5b7880b67c1aa2e0871ce16d5c01cadc7 (diff) | |
| download | gem5-90ed58bcb1791b36e2ecc585ff91b842b1d89610.tar.xz | |
dev-arm: Implement GIC-400 model from GicV2
Implementation registers for the GICv2 model currently hold values
referring to a GIC-400 implementation. This patch is making them
parametrizable so that it is possible to instantiate a GIC-400 model.
The patch is also modifying Realview platform to use new GIC-400 model
in lieau of GICv2.
Change-Id: I446db8c796ee3c2708af91e9139f0a6e7947321b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15277
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev/arm/gic_v2.hh')
| -rw-r--r-- | src/dev/arm/gic_v2.hh | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh index 49465ad56..f9b66b827 100644 --- a/src/dev/arm/gic_v2.hh +++ b/src/dev/arm/gic_v2.hh @@ -75,14 +75,9 @@ class GicV2 : public BaseGic, public BaseGicRegisters DIST_SIZE = 0x1000, }; - /** - * As defined in: - * "ARM Generic Interrupt Controller Architecture" version 2.0 - * "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1 - */ - static constexpr uint32_t GICD_400_PIDR_VALUE = 0x002bb490; - static constexpr uint32_t GICD_400_IIDR_VALUE = 0x200143B; - static constexpr uint32_t GICC_400_IIDR_VALUE = 0x202143B; + const uint32_t gicdPIDR; + const uint32_t gicdIIDR; + const uint32_t giccIIDR; static const AddrRange GICD_IGROUPR; // interrupt group (unimplemented) static const AddrRange GICD_ISENABLER; // interrupt set enable |