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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-15 11:45:53 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-22 08:49:00 +0000 |
| commit | bd8c9614da06899f81fd6d64834db56e4411a728 (patch) | |
| tree | 64030b674607f82555e0168534ef1cc869f6825f /src/dev/arm/gic_v3_its.hh | |
| parent | 8e73f1d497f8586271841750b800e60c054026ec (diff) | |
| download | gem5-bd8c9614da06899f81fd6d64834db56e4411a728.tar.xz | |
dev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR/BASER)
For those registers (GITS_CWRITER, GITS_READR and GITS_CBASER)
Bits [63:32] and bits [31:0] are accessible separately.
Change-Id: Ibf60b5e4fd20efb21a63570e6012862e37946877
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20256
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/dev/arm/gic_v3_its.hh')
| -rw-r--r-- | src/dev/arm/gic_v3_its.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/dev/arm/gic_v3_its.hh b/src/dev/arm/gic_v3_its.hh index e09f712be..dae18d516 100644 --- a/src/dev/arm/gic_v3_its.hh +++ b/src/dev/arm/gic_v3_its.hh @@ -149,12 +149,16 @@ class Gicv3Its : public BasicPioDevice // Command read/write, (CREADR, CWRITER) BitUnion64(CRDWR) + Bitfield<63, 32> high; + Bitfield<31, 0> low; Bitfield<19, 5> offset; Bitfield<0> retry; Bitfield<0> stalled; EndBitUnion(CRDWR) BitUnion64(CBASER) + Bitfield<63, 32> high; + Bitfield<31, 0> low; Bitfield<63> valid; Bitfield<61, 59> innerCache; Bitfield<55, 53> outerCache; |