dev-arm: cleanup of gicv3 code

Change-Id: I9aba90022f6408838c4ab87c6b90bba438752e53
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16222
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

1 files changed, 30 insertions, 32 deletions

diff --git a/src/dev/arm/gic_v3_redistributor.hh b/src/dev/arm/gic_v3_redistributor.hh
index 664173641..578cba105 100644
--- a/src/dev/arm/gic_v3_redistributor.hh
+++ b/src/dev/arm/gic_v3_redistributor.hh
@@ -35,8 +35,8 @@
 #include "dev/arm/gic_v3.hh"
 #include "sim/serialize.hh"
 
-class Gicv3Distributor;
 class Gicv3CPUInterface;
+class Gicv3Distributor;
 
 class Gicv3Redistributor : public Serializable
 {
@@ -56,14 +56,14 @@ class Gicv3Redistributor : public Serializable
      * GICv3 defines 2 contiguous 64KB frames for each redistributor.
      * Order of frames must be RD_base, SGI_base.
      */
-    static const uint32_t RD_base = 0x0;
+    static const uint32_t RD_base  = 0x0;
     static const uint32_t SGI_base = 0x10000;
 
     enum {
         // Control Register
         GICR_CTLR  = RD_base + 0x0000,
         // Implementer Identification Register
-        GICR_IIDR = RD_base + 0x0004,
+        GICR_IIDR  = RD_base + 0x0004,
         // Type Register
         GICR_TYPER = RD_base + 0x0008,
         // Wake Register
@@ -99,21 +99,21 @@ class Gicv3Redistributor : public Serializable
         // Interrupt Clear-Enable Register 0
         GICR_ICENABLER0 = SGI_base + 0x0180,
         // Interrupt Set-Pending Register 0
-        GICR_ISPENDR0 = SGI_base + 0x0200,
+        GICR_ISPENDR0   = SGI_base + 0x0200,
         // Interrupt Clear-Pending Register 0
-        GICR_ICPENDR0 = SGI_base + 0x0280,
+        GICR_ICPENDR0   = SGI_base + 0x0280,
         // Interrupt Set-Active Register 0
         GICR_ISACTIVER0 = SGI_base + 0x0300,
         // Interrupt Clear-Active Register 0
         GICR_ICACTIVER0 = SGI_base + 0x0380,
         // SGI Configuration Register
-        GICR_ICFGR0 = SGI_base + 0x0c00,
+        GICR_ICFGR0     = SGI_base + 0x0c00,
         // PPI Configuration Register
-        GICR_ICFGR1 = SGI_base + 0x0c04,
+        GICR_ICFGR1     = SGI_base + 0x0c04,
         // Interrupt Group Modifier Register 0
-        GICR_IGRPMODR0 = SGI_base + 0x0d00,
+        GICR_IGRPMODR0  = SGI_base + 0x0d00,
         // Non-secure Access Control Register
-        GICR_NSACR = SGI_base + 0x0e00,
+        GICR_NSACR      = SGI_base + 0x0e00,
     };
 
     // Interrupt Priority Registers
@@ -164,9 +164,9 @@ class Gicv3Redistributor : public Serializable
     std::vector<LPIConfigurationTableEntry> lpiConfigurationTable;
 
     static const uint32_t GICR_CTLR_ENABLE_LPIS = 1 << 0;
-    static const uint32_t GICR_CTLR_DPG0 = 1 << 24;
+    static const uint32_t GICR_CTLR_DPG0   = 1 << 24;
     static const uint32_t GICR_CTLR_DPG1NS = 1 << 25;
-    static const uint32_t GICR_CTLR_DPG1S = 1 << 26;
+    static const uint32_t GICR_CTLR_DPG1S  = 1 << 26;
 
   public:
 
@@ -181,39 +181,37 @@ class Gicv3Redistributor : public Serializable
 
     static const uint32_t SMALLEST_LPI_ID = 8192;
 
-    Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id);
-    ~Gicv3Redistributor();
-    void init();
-    void initState();
 
-    uint64_t read(Addr addr, size_t size, bool is_secure_access);
-    void write(Addr addr, uint64_t data, size_t size,
-               bool is_secure_access);
-    void sendPPInt(uint32_t int_id);
-    void sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns);
-    void serialize(CheckpointOut & cp) const override;
-    void unserialize(CheckpointIn & cp) override;
-    uint32_t getAffinity();
+    void activateIRQ(uint32_t int_id);
+    bool canBeSelectedFor1toNInterrupt(Gicv3::GroupId group) const;
+    void deactivateIRQ(uint32_t int_id);
 
-    Gicv3CPUInterface *
+    inline Gicv3CPUInterface *
     getCPUInterface() const
     {
         return cpuInterface;
     }
 
-    bool canBeSelectedFor1toNInterrupt(Gicv3::GroupId group);
+    Gicv3::GroupId getIntGroup(int int_id) const;
+    Gicv3::IntStatus intStatus(uint32_t int_id) const;
     void setClrLPI(uint64_t data, bool set);
-
-  protected:
-
     void reset();
+    void sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns);
+    void serialize(CheckpointOut & cp) const override;
+    void unserialize(CheckpointIn & cp) override;
     void update();
     void updateAndInformCPUInterface();
-    Gicv3::IntStatus intStatus(uint32_t int_id);
-    Gicv3::GroupId getIntGroup(int int_id);
-    void activateIRQ(uint32_t int_id);
-    void deactivateIRQ(uint32_t int_id);
+
+  public:
+
+    Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id);
     void invalLpiConfig(uint32_t lpi_entry_index);
+    uint32_t getAffinity() const;
+    void init();
+    void initState();
+    uint64_t read(Addr addr, size_t size, bool is_secure_access);
+    void sendPPInt(uint32_t int_id);
+    void write(Addr addr, uint64_t data, size_t size, bool is_secure_access);
 };
 
 #endif //__DEV_ARM_GICV3_REDISTRIBUTOR_H__