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| author | Adrien Pesle <adrien.pesle@arm.com> | 2018-09-03 16:43:24 +0200 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-01 08:28:51 +0000 |
| commit | 058e2cec7c56bf0549efff1df5974799c41cd1be (patch) | |
| tree | 0be3f4915fae6c32e017735bb4bd36cd34c6e2d4 /src/dev/arm/hdlcd.hh | |
| parent | cf20e8211e2c3f1b2085c949a1e992a1f5d1071c (diff) | |
| download | gem5-058e2cec7c56bf0549efff1df5974799c41cd1be.tar.xz | |
dev-arm: Add basic support for level sensitive SPIs in GICv2
For level sensitive interrupt IRQ line must be cleared when interrupt is
deasserted. This is not the case for edge-trigerred interrupt.
Change-Id: Ib1660da74a296750c0eb9e20878d4ee64bd23130
Reviewed-on: https://gem5-review.googlesource.com/12944
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev/arm/hdlcd.hh')
0 files changed, 0 insertions, 0 deletions