diff options
| author | Bjoern A. Zeeb <baz21@cam.ac.uk> | 2016-05-19 15:19:35 -0500 |
|---|---|---|
| committer | Bjoern A. Zeeb <baz21@cam.ac.uk> | 2016-05-19 15:19:35 -0500 |
| commit | a6b00c07f6ec9dd25c860bc89691e3873f7996c6 (patch) | |
| tree | 5692005b59b3554ded54adeefd500a5bb9f169b9 /src/dev/arm/pl011.cc | |
| parent | 5fa6b68981dd8566bc2808a309f34d40186a74cf (diff) | |
| download | gem5-a6b00c07f6ec9dd25c860bc89691e3873f7996c6.tar.xz | |
arm,dev: PL011 UART_FR read status enhancement
Given we do not simulate a FIFO currently there are only two states
we can be in upon read: empty or full. Properly signal the latter.
Add and sort constants for states in the header file.
Committed by Jason Lowe-Power <power.jg@gmail.com>
Diffstat (limited to 'src/dev/arm/pl011.cc')
| -rw-r--r-- | src/dev/arm/pl011.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc index f0c3d2d98..e00ee8351 100644 --- a/src/dev/arm/pl011.cc +++ b/src/dev/arm/pl011.cc @@ -91,7 +91,8 @@ Pl011::read(PacketPtr pkt) case UART_FR: data = UART_FR_CTS | // Clear To Send - (!term->dataAvailable() ? UART_FR_RXFE : 0) | // RX FIFO Empty + // Given we do not simulate a FIFO we are either empty or full. + (!term->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) | UART_FR_TXFE; // TX FIFO empty DPRINTF(Uart, |