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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-10-17 10:20:45 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-10-17 10:20:45 -0500 |
| commit | 88b811b4efdb4c4defd4fa5a2426a5012939b39c (patch) | |
| tree | 2a2d14bb7d9164bf6d15bf69eeb2c9b7b3015eb7 /src/dev/arm/pl011.cc | |
| parent | c2553745c986c5e89d71fd366fff7fa61b8cbc1e (diff) | |
| download | gem5-88b811b4efdb4c4defd4fa5a2426a5012939b39c.tar.xz | |
dev: Allow additional UART interrupts to be set
This patch allows setting a few additional interrupts for status
changes that should never occur.
Diffstat (limited to 'src/dev/arm/pl011.cc')
| -rw-r--r-- | src/dev/arm/pl011.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc index 2b4225ad5..b47d0e9fb 100644 --- a/src/dev/arm/pl011.cc +++ b/src/dev/arm/pl011.cc @@ -211,10 +211,14 @@ Pl011::write(PacketPtr pkt) case UART_IMSC: imsc = data; - if (imsc.rimim || imsc.ctsmim || imsc.dcdmim || imsc.dsrmim - || imsc.feim || imsc.peim || imsc.beim || imsc.oeim || imsc.rsvd) + if (imsc.feim || imsc.peim || imsc.beim || imsc.oeim || imsc.rsvd) panic("Unknown interrupt enabled\n"); + // rimim, ctsmim, dcdmim, dsrmim can be enabled but are ignored + // they are supposed to interrupt on a change of status in the line + // which we should never have since our terminal is happy to always + // receive bytes. + if (imsc.txim) { DPRINTF(Uart, "Writing to IMSC: TX int enabled, scheduling interruptt\n"); rawInt.txim = 1; |