diff options
author | Gabe Black <gabeblack@google.com> | 2018-10-12 04:58:50 -0700 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2018-10-12 23:45:51 +0000 |
commit | 9125a43f624653e6238dbb8713658cae2c5d43cd (patch) | |
tree | 268bab703026e5d6497492c97b736f125e875c59 /src/dev/arm/rv_ctrl.cc | |
parent | 413b4e7431b20d9b29dbf66d6677a60205ddd357 (diff) | |
download | gem5-9125a43f624653e6238dbb8713658cae2c5d43cd.tar.xz |
arm: Use little endian packet accessors.
We know data is little endian, so we can use those accessors
explicitly.
Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45
Reviewed-on: https://gem5-review.googlesource.com/c/13457
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev/arm/rv_ctrl.cc')
-rw-r--r-- | src/dev/arm/rv_ctrl.cc | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/src/dev/arm/rv_ctrl.cc b/src/dev/arm/rv_ctrl.cc index 954be6597..9f9e51f09 100644 --- a/src/dev/arm/rv_ctrl.cc +++ b/src/dev/arm/rv_ctrl.cc @@ -61,66 +61,66 @@ RealViewCtrl::read(PacketPtr pkt) switch(daddr) { case ProcId0: - pkt->set(params()->proc_id0); + pkt->setLE(params()->proc_id0); break; case ProcId1: - pkt->set(params()->proc_id1); + pkt->setLE(params()->proc_id1); break; case Clock24: Tick clk; clk = SimClock::Float::MHz * curTick() * 24; - pkt->set((uint32_t)(clk)); + pkt->setLE((uint32_t)(clk)); break; case Clock100: Tick clk100; clk100 = SimClock::Float::MHz * curTick() * 100; - pkt->set((uint32_t)(clk100)); + pkt->setLE((uint32_t)(clk100)); break; case Flash: - pkt->set<uint32_t>(0); + pkt->setLE<uint32_t>(0); break; case Clcd: - pkt->set<uint32_t>(0x00001F00); + pkt->setLE<uint32_t>(0x00001F00); break; case Osc0: - pkt->set<uint32_t>(0x00012C5C); + pkt->setLE<uint32_t>(0x00012C5C); break; case Osc1: - pkt->set<uint32_t>(0x00002CC0); + pkt->setLE<uint32_t>(0x00002CC0); break; case Osc2: - pkt->set<uint32_t>(0x00002C75); + pkt->setLE<uint32_t>(0x00002C75); break; case Osc3: - pkt->set<uint32_t>(0x00020211); + pkt->setLE<uint32_t>(0x00020211); break; case Osc4: - pkt->set<uint32_t>(0x00002C75); + pkt->setLE<uint32_t>(0x00002C75); break; case Lock: - pkt->set<uint32_t>(sysLock); + pkt->setLE<uint32_t>(sysLock); break; case Flags: - pkt->set<uint32_t>(flags); + pkt->setLE<uint32_t>(flags); break; case IdReg: - pkt->set<uint32_t>(params()->idreg); + pkt->setLE<uint32_t>(params()->idreg); break; case CfgStat: - pkt->set<uint32_t>(1); + pkt->setLE<uint32_t>(1); break; case CfgData: - pkt->set<uint32_t>(scData); + pkt->setLE<uint32_t>(scData); DPRINTF(RVCTRL, "Read %#x from SCReg\n", scData); break; case CfgCtrl: - pkt->set<uint32_t>(0); // not busy + pkt->setLE<uint32_t>(0); // not busy DPRINTF(RVCTRL, "Read 0 from CfgCtrl\n"); break; default: warn("Tried to read RealView I/O at offset %#x that doesn't exist\n", daddr); - pkt->set<uint32_t>(0); + pkt->setLE<uint32_t>(0); break; } pkt->makeAtomicResponse(); @@ -144,26 +144,26 @@ RealViewCtrl::write(PacketPtr pkt) case Osc4: break; case Lock: - sysLock.lockVal = pkt->get<uint16_t>(); + sysLock.lockVal = pkt->getLE<uint16_t>(); break; case ResetCtl: // Ignore writes to reset control warn_once("Ignoring write to reset control\n"); break; case Flags: - flags = pkt->get<uint32_t>(); + flags = pkt->getLE<uint32_t>(); break; case FlagsClr: flags = 0; break; case CfgData: - scData = pkt->get<uint32_t>(); + scData = pkt->getLE<uint32_t>(); break; case CfgCtrl: { // A request is being submitted to read/write the system control // registers. See // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html - CfgCtrlReg req = pkt->get<uint32_t>(); + CfgCtrlReg req = pkt->getLE<uint32_t>(); if (!req.start) { DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n", req); @@ -195,7 +195,7 @@ RealViewCtrl::write(PacketPtr pkt) case CfgStat: // Weird to write this default: warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n", - daddr, pkt->get<uint32_t>()); + daddr, pkt->getLE<uint32_t>()); break; } pkt->makeAtomicResponse(); |