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| author | Pablo Prieto <pablo.prieto@unican.es> | 2019-06-06 16:33:26 +0200 |
|---|---|---|
| committer | Anthony Gutierrez <anthony.gutierrez@amd.com> | 2019-08-19 17:00:33 +0000 |
| commit | 4bcb6023f1dce368ff28f31f2960b32d16ae77b6 (patch) | |
| tree | 7dbb4c6546db2194c78a2d8e868266e764ee2c48 /src/dev/arm/rv_ctrl.cc | |
| parent | c7f18da6b04bb757bace18f22542c8078ba1b7b2 (diff) | |
| download | gem5-4bcb6023f1dce368ff28f31f2960b32d16ae77b6.tar.xz | |
mem-ruby, arch-hsail: Removed hit latency from VIPERCoalescer
Removed the dcache hit latency from VIPERCoalescer so HSAIL_X86
compiles after commit 496d5ed3e1f7dad42b0c2ebe0050d84621be8f99
Change-Id: I050a58d90f0f6356824c3c3bcb3f0b3c76d145e0
Signed-off-by: Pablo Prieto <pablo.prieto@unican.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19148
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/dev/arm/rv_ctrl.cc')
0 files changed, 0 insertions, 0 deletions