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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2017-01-31 17:11:24 +0000 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-04-03 16:51:46 +0000 |
| commit | 2f14baaabca315e078597e3441bf8cf3dc703264 (patch) | |
| tree | 554addecd71cc0f11855f9ee13adb7b58055f1cc /src/dev/arm/rv_ctrl.hh | |
| parent | bbdd34d62863d2cc870568890dac0eb0f8be358c (diff) | |
| download | gem5-2f14baaabca315e078597e3441bf8cf3dc703264.tar.xz | |
arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handling
The aforementioned registers (Interrupt Processor Targets Registers) are
banked per-CPU, but are read-only. This patch eliminates the per-CPU
storage of these values that are simply computed.
Change-Id: I52cafc2f58e87dd54239a71326c01f4923544689
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2442
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
Diffstat (limited to 'src/dev/arm/rv_ctrl.hh')
0 files changed, 0 insertions, 0 deletions