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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2019-07-25 14:58:54 +0100
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2019-08-07 12:41:34 +0000
commit676d5fe4e882c9d073964a72c619024306fd279a (patch)
treeec35840d82a6ccda5e602c261a1da8718418ee26 /src/dev/arm/smmu_v3_caches.hh
parente33b3aa6692b172f6db5957774a9e0289e81fa5b (diff)
downloadgem5-676d5fe4e882c9d073964a72c619024306fd279a.tar.xz
dev-arm: Perform SMMUv3 CFG Invalidation at device interface
In the current SMMUv3 model, multiple micro/mainTLB are present at the device interface (SMMUv3SlaveInterface), caching translations specific to a device. Those distributed TLBs are checked for a translation before checking for centralized TLBs (shared by devices), like the configuration cache, walk cache etc. This means that if a hit in these TLBs occurs, there won't be a need to enter configuration stage (which is where the STE and CD are retrieved). So if we invalidate a cached configuration (in ConfigCache), we need to invalidate those interface TLB entries as well, otherwise in theory we will keep the same translation even after a change in configuration tables. Change-Id: I4aa36ba8392a530267517bef7562318b282bee25 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel van Tol <michiel.vantol@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19813 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/dev/arm/smmu_v3_caches.hh')
-rw-r--r--src/dev/arm/smmu_v3_caches.hh3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/dev/arm/smmu_v3_caches.hh b/src/dev/arm/smmu_v3_caches.hh
index 060f60e11..50b293cf2 100644
--- a/src/dev/arm/smmu_v3_caches.hh
+++ b/src/dev/arm/smmu_v3_caches.hh
@@ -130,6 +130,8 @@ class SMMUTLB : public SMMUv3BaseCache
bool updStats=true);
void store(const Entry &incoming, AllocPolicy alloc);
+ void invalidateSSID(uint32_t sid, uint32_t ssid);
+ void invalidateSID(uint32_t sid);
void invalidateVA(Addr va, uint16_t asid, uint16_t vmid);
void invalidateVAA(Addr va, uint16_t vmid);
void invalidateASID(uint16_t asid, uint16_t vmid);
@@ -142,6 +144,7 @@ class SMMUTLB : public SMMUv3BaseCache
size_t associativity;
+ size_t pickSetIdx(uint32_t sid, uint32_t ssid) const;
size_t pickSetIdx(Addr va) const;
size_t pickEntryIdxToReplace(const Set &set, AllocPolicy alloc);
};