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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-03 10:45:40 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-07 12:12:55 +0000 |
| commit | 286b6267afde29fcbe7d6aa3950ded6dba9eda1e (patch) | |
| tree | 462a8a9396787fe6932b576d665465143b9f9685 /src/dev/arm/timer_cpulocal.hh | |
| parent | e87a293d1ffa6da38ba8fa145e7dc5128138ab77 (diff) | |
| download | gem5-286b6267afde29fcbe7d6aa3950ded6dba9eda1e.tar.xz | |
dev-arm: Add GICD_SGIR register
The Distributor Software Generated Interrupt Register is implemented
only if affinity routing is disabled. Since this configuration is
currently not supported in gem5, it has to be treated as RES0.
Change-Id: I9ffcb31b26fc17547f74a4f1d43ce72c59786fa8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20630
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev/arm/timer_cpulocal.hh')
0 files changed, 0 insertions, 0 deletions