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| author | Maurice Becker <madnaurice@googlemail.com> | 2018-09-18 10:27:40 +0200 |
|---|---|---|
| committer | MadMaurice <madnaurice@googlemail.com> | 2018-09-18 09:58:46 +0000 |
| commit | 95143897fc9894241c663982496578b67a238be7 (patch) | |
| tree | 920eb601f983f5f68019d20d58b609d9dc84001e /src/dev/arm/ufs_device.cc | |
| parent | 1fdf576ec73f676c1bfa2e2524293deab0f5cd68 (diff) | |
| download | gem5-95143897fc9894241c663982496578b67a238be7.tar.xz | |
Pl011: Added registers UART_RSR/UART_ECR
UART_RSR shows errors with the transmission and UART_ECR can clear
those (according to PL011 Technical Reference Manual Revision r1p4). As
these transmission errors never occur, they are implemented as RAZ/WI.
Both registers exist at the same offset 0x004. RSR is read-only, ECR is
write-only.
Signed-off-by: Maurice Becker <madnaurice@googlemail.com>
Change-Id: Ia9d13c90c65feccf3ecec36a782170755b1e1c02
Reviewed-on: https://gem5-review.googlesource.com/12686
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/dev/arm/ufs_device.cc')
0 files changed, 0 insertions, 0 deletions