dev: Rewrite PCI host functionality

The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).

This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.

PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.

The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.

Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:

  * Configurable configuration space decoding. The number of bits
    dedicated to a device is a prameter, making it possible to support
    both CAM, ECAM, and legacy mappings.

  * Basic interrupt mapping using the interruptLine value from a
    device's configuration space. This behavior is the same as in the
    old implementation. More advanced controllers can override the
    interrupt mapping method to dynamically assign host interrupts to
    PCI devices.

  * Simple (base + addr) remapping from the PCI bus's address space to
    physical addresses for PIO, memory, and DMA.

3 files changed, 20 insertions, 103 deletions

diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index db38b6bbd..78154bcfd 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -45,7 +45,7 @@ from m5.proxy import *
 from ClockDomain import ClockDomain
 from VoltageDomain import VoltageDomain
 from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
-from Pci import PciConfigAll
+from PciHost import *
 from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
 from Ide import *
 from Platform import Platform
@@ -255,10 +255,6 @@ class RealView(Platform):
     type = 'RealView'
     cxx_header = "dev/arm/realview.hh"
     system = Param.System(Parent.any, "system")
-    pci_io_base = Param.Addr(0, "Base address of PCI IO Space")
-    pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
-    pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access"
-            " be compatible with the pci-generic-host or the legacy host bridge?")
     _mem_regions = [(Addr(0), Addr('256MB'))]
 
     def attachPciDevices(self):
@@ -292,6 +288,9 @@ class RealViewPBX(RealView):
     mcc = VExpressMCC()
     dcc = CoreTile2A15DCC()
     gic = Pl390()
+    pci_host = GenericPciHost(
+        conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
+        pci_pio_base=0)
     timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
     timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
     local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
@@ -356,6 +355,7 @@ class RealViewPBX(RealView):
     def attachIO(self, bus):
        self.uart.pio          = bus.master
        self.realview_io.pio   = bus.master
+       self.pci_host.pio      = bus.master
        self.timer0.pio        = bus.master
        self.timer1.pio        = bus.master
        self.clcd.pio          = bus.master
@@ -363,7 +363,6 @@ class RealViewPBX(RealView):
        self.kmi0.pio          = bus.master
        self.kmi1.pio          = bus.master
        self.cf_ctrl.pio       = bus.master
-       self.cf_ctrl.config    = bus.master
        self.cf_ctrl.dma       = bus.slave
        self.dmac_fake.pio     = bus.master
        self.uart1_fake.pio    = bus.master
@@ -471,6 +470,7 @@ class RealViewEB(RealView):
     def attachIO(self, bus):
        self.uart.pio          = bus.master
        self.realview_io.pio   = bus.master
+       self.pci_host.pio      = bus.master
        self.timer0.pio        = bus.master
        self.timer1.pio        = bus.master
        self.clcd.pio          = bus.master
@@ -527,7 +527,6 @@ class RealViewEB(RealView):
 
 class VExpress_EMM(RealView):
     _mem_regions = [(Addr('2GB'), Addr('2GB'))]
-    pci_cfg_base = 0x30000000
     uart = Pl011(pio_addr=0x1c090000, int_num=37)
     realview_io = RealViewCtrl(
         proc_id0=0x14000000, proc_id1=0x14000000,
@@ -535,6 +534,9 @@ class VExpress_EMM(RealView):
     mcc = VExpressMCC()
     dcc = CoreTile2A15DCC()
     gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
+    pci_host = GenericPciHost(
+        conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
+        pci_pio_base=0)
     local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000)
     generic_timer = GenericTimer(int_phys=29, int_virt=27)
     timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
@@ -552,7 +554,6 @@ class VExpress_EMM(RealView):
                             BAR1 = 0x1C1A0100, BAR1Size = '4096B',
                             BAR0LegacyIO = True, BAR1LegacyIO = True)
 
-    pciconfig = PciConfigAll(size='256MB')
     vram           = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
                                   conf_table_reported = False)
     rtc            = PL031(pio_addr=0x1C170000, int_num=36)
@@ -624,6 +625,7 @@ class VExpress_EMM(RealView):
     def attachIO(self, bus):
        self.uart.pio            = bus.master
        self.realview_io.pio     = bus.master
+       self.pci_host.pio        = bus.master
        self.timer0.pio          = bus.master
        self.timer1.pio          = bus.master
        self.clcd.pio            = bus.master
@@ -633,11 +635,8 @@ class VExpress_EMM(RealView):
        self.kmi1.pio            = bus.master
        self.cf_ctrl.pio         = bus.master
        self.cf_ctrl.dma         = bus.slave
-       self.cf_ctrl.config      = bus.master
        self.rtc.pio             = bus.master
-       bus.use_default_range    = True
        self.vram.port           = bus.master
-       self.pciconfig.pio       = bus.default
 
        self.l2x0_fake.pio       = bus.master
        self.uart1_fake.pio      = bus.master
@@ -654,10 +653,8 @@ class VExpress_EMM(RealView):
        # Try to attach the I/O if it exists
        try:
            self.ide.pio         = bus.master
-           self.ide.config      = bus.master
            self.ide.dma         = bus.slave
            self.ethernet.pio    = bus.master
-           self.ethernet.config = bus.master
            self.ethernet.dma    = bus.slave
        except:
            pass
@@ -675,7 +672,6 @@ class VExpress_EMM(RealView):
         self.cf_ctrl.clk_domain       = clkdomain
         self.rtc.clk_domain           = clkdomain
         self.vram.clk_domain          = clkdomain
-        self.pciconfig.clk_domain     = clkdomain
 
         self.l2x0_fake.clk_domain     = clkdomain
         self.uart1_fake.clk_domain    = clkdomain
@@ -690,11 +686,13 @@ class VExpress_EMM(RealView):
         self.energy_ctrl.clk_domain   = clkdomain
 
 class VExpress_EMM64(VExpress_EMM):
-    pci_io_base = 0x2f000000
-    pci_cfg_gen_offsets = True
     # Three memory regions are specified totalling 512GB
     _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
                     (Addr('512GB'), Addr('480GB'))]
+    pci_host = GenericPciHost(
+        conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
+        pci_pio_base=0x2f000000)
+
     def setupBootLoader(self, mem_bus, cur_sys, loc):
         self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
         self.nvmem.port = mem_bus.master
diff --git a/src/dev/arm/realview.cc b/src/dev/arm/realview.cc
index a4c1191b3..2a6bc63f3 100644
--- a/src/dev/arm/realview.cc
+++ b/src/dev/arm/realview.cc
@@ -58,26 +58,12 @@
 using namespace std;
 using namespace TheISA;
 
+
 RealView::RealView(const Params *p)
     : Platform(p), system(p->system), gic(nullptr)
 {}
 
 void
-RealView::initState()
-{
-    Addr junk;
-    bool has_gen_pci_host;
-    has_gen_pci_host = system->kernelSymtab->findAddress("gen_pci_setup", junk);
-
-    if (has_gen_pci_host && !params()->pci_cfg_gen_offsets)
-        warn("Kernel supports generic PCI host but PCI Config offsets "
-                "configured for legacy. Set pci_cfg_gen_offsets to True");
-    if (has_gen_pci_host && !params()->pci_io_base)
-        warn("Kernel supports generic PCI host but PCI IO base is set "
-                "to 0. Set pci_io_base to the start of PCI IO space");
-}
-
-void
 RealView::postConsoleInt()
 {
     warn_once("Don't know what interrupt to post for console.\n");
@@ -103,39 +89,6 @@ RealView::clearPciInt(int line)
     gic->clearInt(line);
 }
 
-Addr
-RealView::pciToDma(Addr pciAddr) const
-{
-    return pciAddr;
-}
-
-
-Addr
-RealView::calcPciConfigAddr(int bus, int dev, int func)
-{
-    if (bus != 0)
-        return ULL(-1);
-
-    Addr cfg_offset = 0;
-    if (params()->pci_cfg_gen_offsets)
-        cfg_offset |= ((func & 7) << 12) | ((dev & 0x1f) << 15);
-    else
-        cfg_offset |= ((func & 7) << 16) | ((dev & 0x1f) << 19);
-    return params()->pci_cfg_base | cfg_offset;
-}
-
-Addr
-RealView::calcPciIOAddr(Addr addr)
-{
-    return params()->pci_io_base + addr;
-}
-
-Addr
-RealView::calcPciMemAddr(Addr addr)
-{
-    return addr;
-}
-
 RealView *
 RealViewParams::create()
 {
diff --git a/src/dev/arm/realview.hh b/src/dev/arm/realview.hh
index 5129069d4..eaaec9425 100644
--- a/src/dev/arm/realview.hh
+++ b/src/dev/arm/realview.hh
@@ -79,49 +79,15 @@ class RealView : public Platform
      */
     RealView(const Params *p);
 
-    /** In init do some checks to help verify we're setup correctly */
-    virtual void initState();
-
     /** Give platform a pointer to interrupt controller */
     void setGic(BaseGic *_gic) { gic = _gic; }
 
-    /**
-     * Cause the cpu to post a serial interrupt to the CPU.
-     */
-    virtual void postConsoleInt();
-
-    /**
-     * Clear a posted CPU interrupt
-     */
-    virtual void clearConsoleInt();
-
-    /**
-     * Cause the chipset to post a cpi interrupt to the CPU.
-     */
-    virtual void postPciInt(int line);
-
-    /**
-     * Clear a posted PCI->CPU interrupt
-     */
-    virtual void clearPciInt(int line);
-
-
-    virtual Addr pciToDma(Addr pciAddr) const;
-
-    /**
-     * Calculate the configuration address given a bus/dev/func.
-     */
-    virtual Addr calcPciConfigAddr(int bus, int dev, int func);
+  public: // Public Platform interfaces
+    void postConsoleInt() override;
+    void clearConsoleInt() override;
 
-    /**
-     * Calculate the address for an IO location on the PCI bus.
-     */
-    virtual Addr calcPciIOAddr(Addr addr);
-
-    /**
-     * Calculate the address for a memory location on the PCI bus.
-     */
-    virtual Addr calcPciMemAddr(Addr addr);
+    void postPciInt(int line) override;
+    void clearPciInt(int line) override;
 };
 
 #endif // __DEV_ARM_RealView_HH__