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authorBjoern A. Zeeb <baz21@cam.ac.uk>2016-10-15 15:11:04 -0500
committerBjoern A. Zeeb <baz21@cam.ac.uk>2016-10-15 15:11:04 -0500
commit28c84d28861a1b143d0c0c9087a77e931a233e67 (patch)
tree0658ee736dfa0d01ea34a55620e5fa3dcf13f2e6 /src/dev/arm
parent976ef444b83d9c2ab1cff5cf95434d349e3c3161 (diff)
downloadgem5-28c84d28861a1b143d0c0c9087a77e931a233e67.tar.xz
arm, dev: pl011 console interactivity
Improve PL011 console interactivity Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/dev/arm')
-rw-r--r--src/dev/arm/pl011.cc10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc
index e00ee8351..40f34e1fd 100644
--- a/src/dev/arm/pl011.cc
+++ b/src/dev/arm/pl011.cc
@@ -86,6 +86,11 @@ Pl011::read(PacketPtr pkt)
// Since we don't simulate a FIFO for incoming data, we
// assume it's empty and clear RXINTR and RTINTR.
clearInterrupts(UART_RXINTR | UART_RTINTR);
+ if (term->dataAvailable()) {
+ DPRINTF(Uart, "Re-raising interrupt due to more data "
+ "after UART_DR read\n");
+ dataAvailable();
+ }
}
break;
case UART_FR:
@@ -224,6 +229,11 @@ Pl011::write(PacketPtr pkt)
case UART_ICR:
DPRINTF(Uart, "Clearing interrupts 0x%x\n", data);
clearInterrupts(data);
+ if (term->dataAvailable()) {
+ DPRINTF(Uart, "Re-raising interrupt due to more data after "
+ "UART_ICR write\n");
+ dataAvailable();
+ }
break;
default:
panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr);