base: Declare a type for context IDs

Context IDs used to be declared as ad hoc (usually as int). This
changeset introduces a typedef for ContextIDs and a constant for
invalid context IDs.

5 files changed, 14 insertions, 14 deletions

diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc
index 5a21f6cec..fb1711c92 100644
--- a/src/dev/arm/gic_pl390.cc
+++ b/src/dev/arm/gic_pl390.cc
@@ -135,7 +135,7 @@ Pl390::readDistributor(PacketPtr pkt)
 {
     Addr daddr = pkt->getAddr() - distAddr;
 
-    int ctx_id = pkt->req->contextId();
+    ContextID ctx_id = pkt->req->contextId();
 
     DPRINTF(GIC, "gic distributor read register %#x\n", daddr);
 
@@ -269,7 +269,7 @@ Pl390::readCpu(PacketPtr pkt)
     Addr daddr = pkt->getAddr() - cpuAddr;
 
     assert(pkt->req->hasContextId());
-    int ctx_id = pkt->req->contextId();
+    ContextID ctx_id = pkt->req->contextId();
     assert(ctx_id < sys->numRunningContexts());
 
     DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr,
@@ -356,7 +356,7 @@ Pl390::writeDistributor(PacketPtr pkt)
     Addr daddr = pkt->getAddr() - distAddr;
 
     assert(pkt->req->hasContextId());
-    int ctx_id = pkt->req->contextId();
+    ContextID ctx_id = pkt->req->contextId();
 
     uint32_t pkt_data M5_VAR_USED;
     switch (pkt->getSize())
@@ -496,7 +496,7 @@ Pl390::writeCpu(PacketPtr pkt)
     Addr daddr = pkt->getAddr() - cpuAddr;
 
     assert(pkt->req->hasContextId());
-    int ctx_id = pkt->req->contextId();
+    ContextID ctx_id = pkt->req->contextId();
     IAR iar;
 
     DPRINTF(GIC, "gic cpu write register cpu:%d %#x val: %#x\n",
@@ -546,7 +546,7 @@ Pl390::writeCpu(PacketPtr pkt)
 }
 
 void
-Pl390::softInt(int ctx_id, SWI swi)
+Pl390::softInt(ContextID ctx_id, SWI swi)
 {
     switch (swi.list_type) {
       case 1:
diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh
index 1adad6c9a..17946145f 100644
--- a/src/dev/arm/gic_pl390.hh
+++ b/src/dev/arm/gic_pl390.hh
@@ -210,7 +210,7 @@ class Pl390 : public BaseGic
     /** software generated interrupt
      * @param data data to decode that indicates which cpus to interrupt
      */
-    void softInt(int ctx_id, SWI swi);
+    void softInt(ContextID ctx_id, SWI swi);
 
     /** See if some processor interrupt flags need to be enabled/disabled
      * @param hint which set of interrupts needs to be checked
diff --git a/src/dev/arm/timer_cpulocal.cc b/src/dev/arm/timer_cpulocal.cc
index ac02d099f..11ae3b3d2 100644
--- a/src/dev/arm/timer_cpulocal.cc
+++ b/src/dev/arm/timer_cpulocal.cc
@@ -75,7 +75,7 @@ CpuLocalTimer::read(PacketPtr pkt)
     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
     assert(pkt->getSize() == 4);
     Addr daddr = pkt->getAddr() - pioAddr;
-    int cpu_id = pkt->req->contextId();
+    ContextID cpu_id = pkt->req->contextId();
     DPRINTF(Timer, "Reading from CpuLocalTimer at offset: %#x\n", daddr);
     assert(cpu_id >= 0);
     assert(cpu_id < CPU_MAX);
@@ -153,7 +153,7 @@ CpuLocalTimer::write(PacketPtr pkt)
     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
     assert(pkt->getSize() == 4);
     Addr daddr = pkt->getAddr() - pioAddr;
-    int cpu_id = pkt->req->contextId();
+    ContextID cpu_id = pkt->req->contextId();
     DPRINTF(Timer, "Writing to CpuLocalTimer at offset: %#x\n", daddr);
     assert(cpu_id >= 0);
     assert(cpu_id < CPU_MAX);
diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc
index f4a3e8c3f..71d1d3bb6 100644
--- a/src/dev/arm/vgic.cc
+++ b/src/dev/arm/vgic.cc
@@ -90,7 +90,7 @@ VGic::readVCpu(PacketPtr pkt)
 {
     Addr daddr = pkt->getAddr() - vcpuAddr;
 
-    int ctx_id = pkt->req->contextId();
+    ContextID ctx_id = pkt->req->contextId();
     assert(ctx_id < VGIC_CPU_MAX);
     struct vcpuIntData *vid = &vcpuData[ctx_id];
 
@@ -134,7 +134,7 @@ VGic::readCtrl(PacketPtr pkt)
 {
     Addr daddr = pkt->getAddr() - hvAddr;
 
-    int ctx_id = pkt->req->contextId();
+    ContextID ctx_id = pkt->req->contextId();
 
     DPRINTF(VGIC, "VGIC HVCtrl read register %#x\n", daddr);
 
@@ -228,7 +228,7 @@ VGic::writeVCpu(PacketPtr pkt)
 {
     Addr daddr = pkt->getAddr() - vcpuAddr;
 
-    int ctx_id = pkt->req->contextId();
+    ContextID ctx_id = pkt->req->contextId();
     assert(ctx_id < VGIC_CPU_MAX);
     struct vcpuIntData *vid = &vcpuData[ctx_id];
 
@@ -275,7 +275,7 @@ VGic::writeCtrl(PacketPtr pkt)
 {
     Addr daddr = pkt->getAddr() - hvAddr;
 
-    int ctx_id = pkt->req->contextId();
+    ContextID ctx_id = pkt->req->contextId();
 
     DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n", daddr, pkt->get<uint32_t>());
 
@@ -380,7 +380,7 @@ VGic::unPostMaintInt(uint32_t cpu)
  * This may raise a maintenance interrupt.
  */
 void
-VGic::updateIntState(int ctx_id)
+VGic::updateIntState(ContextID ctx_id)
 {
     // @todo This should update APRs!
 
diff --git a/src/dev/arm/vgic.hh b/src/dev/arm/vgic.hh
index ac88f842f..d44afd7a9 100644
--- a/src/dev/arm/vgic.hh
+++ b/src/dev/arm/vgic.hh
@@ -222,7 +222,7 @@ class VGic : public PioDevice
     Tick writeVCpu(PacketPtr pkt);
     Tick writeCtrl(PacketPtr pkt);
 
-    void updateIntState(int ctx_id);
+    void updateIntState(ContextID ctx_id);
     uint32_t getMISR(struct vcpuIntData *vid);
     void postVInt(uint32_t cpu, Tick when);
     void unPostVInt(uint32_t cpu);