diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-07-23 16:34:26 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-07-25 12:49:12 +0000 |
| commit | 404b86813e73762cdce537c440abb16f6ab1bb97 (patch) | |
| tree | 43724a75480ce9645bd00e63ca2ad4243541bcfc /src/dev/arm | |
| parent | e71e2d6a35233250ad05b358c27cad5a05609d55 (diff) | |
| download | gem5-404b86813e73762cdce537c440abb16f6ab1bb97.tar.xz | |
dev-arm: TnSZ fields need to be cached in SMMUv3::ConfigCache
Otherwise a hit after a table walk will result in a 0 value being
read from the ConfigCache.
Change-Id: I9813998acce44c93c5ce203f252ca80c10ba8f38
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19631
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/dev/arm')
| -rw-r--r-- | src/dev/arm/smmu_v3_caches.hh | 2 | ||||
| -rw-r--r-- | src/dev/arm/smmu_v3_transl.cc | 5 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/dev/arm/smmu_v3_caches.hh b/src/dev/arm/smmu_v3_caches.hh index ce5bb45a9..060f60e11 100644 --- a/src/dev/arm/smmu_v3_caches.hh +++ b/src/dev/arm/smmu_v3_caches.hh @@ -252,6 +252,8 @@ class ConfigCache : public SMMUv3BaseCache uint16_t vmid; uint8_t stage1_tg; uint8_t stage2_tg; + uint8_t t0sz; + uint8_t s2t0sz; }; ConfigCache(unsigned numEntries, unsigned _associativity, diff --git a/src/dev/arm/smmu_v3_transl.cc b/src/dev/arm/smmu_v3_transl.cc index 84ca5a7c2..c1d998ea0 100644 --- a/src/dev/arm/smmu_v3_transl.cc +++ b/src/dev/arm/smmu_v3_transl.cc @@ -532,6 +532,9 @@ SMMUTranslationProcess::configCacheLookup(Yield &yield, TranslContext &tc) tc.stage1TranslGranule = e->stage1_tg; tc.stage2TranslGranule = e->stage2_tg; + tc.t0sz = e->t0sz; + tc.s2t0sz = e->s2t0sz; + return true; } @@ -555,6 +558,8 @@ SMMUTranslationProcess::configCacheUpdate(Yield &yield, e.vmid = tc.vmid; e.stage1_tg = tc.stage1TranslGranule; e.stage2_tg = tc.stage2TranslGranule; + e.t0sz = tc.t0sz; + e.s2t0sz = tc.s2t0sz; doSemaphoreDown(yield, smmu.configSem); |