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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-07-22 17:38:29 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-07-25 12:49:27 +0000 |
| commit | af1838be8d1efbbbb7133262f23f9f757033589d (patch) | |
| tree | b92975b101bbf556e837e3f7c415df4217fa7006 /src/dev/arm | |
| parent | 404b86813e73762cdce537c440abb16f6ab1bb97 (diff) | |
| download | gem5-af1838be8d1efbbbb7133262f23f9f757033589d.tar.xz | |
dev-arm: Define enum masks for SMMU_CR0 register
The configuration register is a vital register in the SMMU, and using
enum masks will make the code more readable/understandable
Change-Id: Ia117db56c457fe876ae38be391c386e502f34384
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19632
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/dev/arm')
| -rw-r--r-- | src/dev/arm/smmu_v3_defs.hh | 9 | ||||
| -rw-r--r-- | src/dev/arm/smmu_v3_transl.cc | 3 |
2 files changed, 10 insertions, 2 deletions
diff --git a/src/dev/arm/smmu_v3_defs.hh b/src/dev/arm/smmu_v3_defs.hh index 991e90c7b..d993fd715 100644 --- a/src/dev/arm/smmu_v3_defs.hh +++ b/src/dev/arm/smmu_v3_defs.hh @@ -311,6 +311,15 @@ struct ContextDescriptor uint64_t _pad[3]; }; +enum { + CR0_SMMUEN_MASK = 0x1, + CR0_PRIQEN_MASK = 0x2, + CR0_EVENTQEN_MASK = 0x4, + CR0_CMDQEN_MASK = 0x8, + CR0_ATSCHK_MASK = 0x10, + CR0_VMW_MASK = 0x1C0, +}; + enum SMMUCommandType { CMD_PRF_CONFIG = 0x1000, CMD_PRF_ADDR = 0x1001, diff --git a/src/dev/arm/smmu_v3_transl.cc b/src/dev/arm/smmu_v3_transl.cc index c1d998ea0..d7d576883 100644 --- a/src/dev/arm/smmu_v3_transl.cc +++ b/src/dev/arm/smmu_v3_transl.cc @@ -155,8 +155,7 @@ SMMUTranslationProcess::main(Yield &yield) recvTick = curTick(); - - if (!(smmu.regs.cr0 & 0x1)) { + if (!(smmu.regs.cr0 & CR0_SMMUEN_MASK)) { // SMMU disabled doDelay(yield, Cycles(1)); completeTransaction(yield, bypass(request.addr)); |