dev-arm, configs: Remove RealViewPBX platform

This is an old unused platform. We should support VExpress_GEM5 based
platforms only.

Change-Id: If9c29047b2d068992dfbbe0dc268c70b788cce5f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21601
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

1 files changed, 0 insertions, 136 deletions

diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index fc26a017d..3586f20ec 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -613,142 +613,6 @@ class RealView(Platform):
         cpu.append(FdtPropertyWords("cpu-release-addr", \
                                     state.addrCells(0x8000fff8)))
 
-# Reference for memory map and interrupt number
-# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
-# Chapter 4: Programmer's Reference
-class RealViewPBX(RealView):
-    uart = Pl011(pio_addr=0x10009000, int_num=44)
-    realview_io = RealViewCtrl(pio_addr=0x10000000)
-    mcc = VExpressMCC()
-    dcc = CoreTile2A15DCC()
-    gic = Gic400(cpu_addr=0x1f000100, dist_addr=0x1f001000, cpu_size=0x100)
-    pci_host = GenericPciHost(
-        conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
-        pci_pio_base=0)
-    timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
-    timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
-    global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200)
-    local_cpu_timer = CpuLocalTimer(int_timer=ArmPPI(num=29),
-                                    int_watchdog=ArmPPI(num=30),
-                                    pio_addr=0x1f000600)
-    clcd = Pl111(pio_addr=0x10020000, int_num=55)
-    kmi0   = Pl050(pio_addr=0x10006000, int_num=52, ps2=PS2Keyboard())
-    kmi1   = Pl050(pio_addr=0x10007000, int_num=53, ps2=PS2TouchKit())
-    a9scu  = A9SCU(pio_addr=0x1f000000)
-    cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
-                            io_shift = 1, ctrl_offset = 2, Command = 0x1,
-                            BAR0 = 0x18000000, BAR0Size = '16B',
-                            BAR1 = 0x18000100, BAR1Size = '1B',
-                            BAR0LegacyIO = True, BAR1LegacyIO = True)
-
-
-    l2x0_fake     = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
-    flash_fake    = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
-                            fake_mem=True)
-    dmac_fake     = AmbaFake(pio_addr=0x10030000)
-    uart1_fake    = AmbaFake(pio_addr=0x1000a000)
-    uart2_fake    = AmbaFake(pio_addr=0x1000b000)
-    uart3_fake    = AmbaFake(pio_addr=0x1000c000)
-    smc_fake      = AmbaFake(pio_addr=0x100e1000)
-    sp810_fake    = AmbaFake(pio_addr=0x10001000, ignore_access=True)
-    watchdog_fake = AmbaFake(pio_addr=0x10010000)
-    gpio0_fake    = AmbaFake(pio_addr=0x10013000)
-    gpio1_fake    = AmbaFake(pio_addr=0x10014000)
-    gpio2_fake    = AmbaFake(pio_addr=0x10015000)
-    ssp_fake      = AmbaFake(pio_addr=0x1000d000)
-    sci_fake      = AmbaFake(pio_addr=0x1000e000)
-    aaci_fake     = AmbaFake(pio_addr=0x10004000)
-    mmc_fake      = AmbaFake(pio_addr=0x10005000)
-    rtc           = PL031(pio_addr=0x10017000, int_num=42)
-    energy_ctrl   = EnergyCtrl(pio_addr=0x1000f000)
-
-
-    # Attach I/O devices that are on chip and also set the appropriate
-    # ranges for the bridge
-    def attachOnChipIO(self, bus, bridge):
-       self.gic.pio = bus.master
-       self.l2x0_fake.pio = bus.master
-       self.a9scu.pio = bus.master
-       self.global_timer.pio = bus.master
-       self.local_cpu_timer.pio = bus.master
-       # Bridge ranges based on excluding what is part of on-chip I/O
-       # (gic, l2x0, a9scu, local_cpu_timer)
-       bridge.ranges = [AddrRange(self.realview_io.pio_addr,
-                                  self.a9scu.pio_addr - 1),
-                        AddrRange(self.flash_fake.pio_addr,
-                                  self.flash_fake.pio_addr + \
-                                  self.flash_fake.pio_size - 1)]
-
-    # Set the clock domain for IO objects that are considered
-    # to be "close" to the cores.
-    def onChipIOClkDomain(self, clkdomain):
-        self.gic.clk_domain             = clkdomain
-        self.l2x0_fake.clk_domain       = clkdomain
-        self.a9scu.clkdomain            = clkdomain
-        self.local_cpu_timer.clk_domain = clkdomain
-
-    # Attach I/O devices to specified bus object.  Can't do this
-    # earlier, since the bus object itself is typically defined at the
-    # System level.
-    def attachIO(self, bus):
-       self.uart.pio          = bus.master
-       self.realview_io.pio   = bus.master
-       self.pci_host.pio      = bus.master
-       self.timer0.pio        = bus.master
-       self.timer1.pio        = bus.master
-       self.clcd.pio          = bus.master
-       self.clcd.dma          = bus.slave
-       self.kmi0.pio          = bus.master
-       self.kmi1.pio          = bus.master
-       self.cf_ctrl.pio       = bus.master
-       self.cf_ctrl.dma       = bus.slave
-       self.dmac_fake.pio     = bus.master
-       self.uart1_fake.pio    = bus.master
-       self.uart2_fake.pio    = bus.master
-       self.uart3_fake.pio    = bus.master
-       self.smc_fake.pio      = bus.master
-       self.sp810_fake.pio    = bus.master
-       self.watchdog_fake.pio = bus.master
-       self.gpio0_fake.pio    = bus.master
-       self.gpio1_fake.pio    = bus.master
-       self.gpio2_fake.pio    = bus.master
-       self.ssp_fake.pio      = bus.master
-       self.sci_fake.pio      = bus.master
-       self.aaci_fake.pio     = bus.master
-       self.mmc_fake.pio      = bus.master
-       self.rtc.pio           = bus.master
-       self.flash_fake.pio    = bus.master
-       self.energy_ctrl.pio   = bus.master
-
-    # Set the clock domain for IO objects that are considered
-    # to be "far" away from the cores.
-    def offChipIOClkDomain(self, clkdomain):
-        self.uart.clk_domain          = clkdomain
-        self.realview_io.clk_domain   = clkdomain
-        self.timer0.clk_domain        = clkdomain
-        self.timer1.clk_domain        = clkdomain
-        self.clcd.clk_domain          = clkdomain
-        self.kmi0.clk_domain          = clkdomain
-        self.kmi1.clk_domain          = clkdomain
-        self.cf_ctrl.clk_domain       = clkdomain
-        self.dmac_fake.clk_domain     = clkdomain
-        self.uart1_fake.clk_domain    = clkdomain
-        self.uart2_fake.clk_domain    = clkdomain
-        self.uart3_fake.clk_domain    = clkdomain
-        self.smc_fake.clk_domain      = clkdomain
-        self.sp810_fake.clk_domain    = clkdomain
-        self.watchdog_fake.clk_domain = clkdomain
-        self.gpio0_fake.clk_domain    = clkdomain
-        self.gpio1_fake.clk_domain    = clkdomain
-        self.gpio2_fake.clk_domain    = clkdomain
-        self.ssp_fake.clk_domain      = clkdomain
-        self.sci_fake.clk_domain      = clkdomain
-        self.aaci_fake.clk_domain     = clkdomain
-        self.mmc_fake.clk_domain      = clkdomain
-        self.rtc.clk_domain           = clkdomain
-        self.flash_fake.clk_domain    = clkdomain
-        self.energy_ctrl.clk_domain   = clkdomain
-
 class VExpress_EMM(RealView):
     _mem_regions = [ AddrRange('2GB', size='2GB') ]