MEM: Explicit ports and Python binding on CopyEngine

The copy-engine ports were previously created implicitly and bound
based on the dma port peer rather than relying on the normal Python
binding (connectPorts) being called explicitly. This patch makes the
copy engine port similar to all other ports in that they are visibly
in the Python class and bound using the normal explicit calls through
Python.

1 files changed, 15 insertions, 2 deletions

diff --git a/src/dev/copy_engine.hh b/src/dev/copy_engine.hh
index 581d3c80b..65a3ac82d 100644
--- a/src/dev/copy_engine.hh
+++ b/src/dev/copy_engine.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2008 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -82,7 +94,7 @@ class CopyEngine : public PciDev
       public:
         CopyEngineChannel(CopyEngine *_ce, int cid);
         virtual ~CopyEngineChannel();
-        void init();
+        Port *getPort();
 
         std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); }
         virtual Tick read(PacketPtr pkt)
@@ -183,7 +195,8 @@ class CopyEngine : public PciDev
     ~CopyEngine();
 
     void regStats();
-    void init();
+
+    virtual Port *getPort(const std::string &if_name, int idx = -1);
 
     virtual Tick read(PacketPtr pkt);
     virtual Tick write(PacketPtr pkt);