DMA: Refactor the DMA device and align timing and atomic

This patch does a bunch of house-keeping updates on the DMA, including
indentation, and formatting, but most importantly breaks out the
response handling such that it can be shared between the atomic and
timing modes. It also removes a potential bug caused by the atomic
handling of responses only deleting the allocated request (pkt->req)
once the DMA action completes instead of doing so for every packet.

Before this patch, the handling of responses was near identical for
atomic and timing, but the code was simply duplicated. With this
patch, the handleResp method deals with the responses in both cases.

There are further updates to make after removing the NACKs, but that
will be part of a separate follow-up patch. This patch does not change
the behaviour of any regression.

1 files changed, 26 insertions, 17 deletions

diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index 691a21749..48c3f9c61 100644
--- a/src/dev/dma_device.hh
+++ b/src/dev/dma_device.hh
@@ -44,6 +44,8 @@
 #ifndef __DEV_DMA_DEVICE_HH__
 #define __DEV_DMA_DEVICE_HH__
 
+#include <deque>
+
 #include "dev/io_device.hh"
 #include "params/DmaDevice.hh"
 
@@ -71,7 +73,9 @@ class DmaPort : public MasterPort
     };
 
     MemObject *device;
-    std::list<PacketPtr> transmitList;
+
+    /** Use a deque as we never to any insertion or removal in the middle */
+    std::deque<PacketPtr> transmitList;
 
     /** The system that device/port are in. This is used to select which mode
      * we are currently operating in. */
@@ -81,21 +85,32 @@ class DmaPort : public MasterPort
     MasterID masterId;
 
     /** Number of outstanding packets the dma port has. */
-    int pendingCount;
+    uint32_t pendingCount;
 
     /** If we need to drain, keep the drain event around until we're done
      * here.*/
     Event *drainEvent;
 
-    /** If the port is currently waiting for a retry before it can send whatever
-     * it is that it's sending. */
+    /** If the port is currently waiting for a retry before it can
+     * send whatever it is that it's sending. */
     bool inRetry;
 
-    virtual bool recvTimingResp(PacketPtr pkt);
-
-    virtual void recvRetry() ;
-
-    void queueDma(PacketPtr pkt, bool front = false);
+    /**
+     * Handle a response packet by updating the corresponding DMA
+     * request state to reflect the bytes received, and also update
+     * the pending request counter. If the DMA request that this
+     * packet is part of is complete, then signal the completion event
+     * if present, potentially with a delay added to it.
+     *
+     * @param pkt Response packet to handler
+     * @param delay Additional delay for scheduling the completion event
+     */
+    void handleResp(PacketPtr pkt, Tick delay = 0);
+
+    bool recvTimingResp(PacketPtr pkt);
+    void recvRetry() ;
+
+    void queueDma(PacketPtr pkt);
     void sendDma();
 
   public:
@@ -105,7 +120,7 @@ class DmaPort : public MasterPort
     void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
                    uint8_t *data, Tick delay, Request::Flags flag = 0);
 
-    bool dmaPending() { return pendingCount > 0; }
+    bool dmaPending() const { return pendingCount > 0; }
 
     unsigned cacheBlockSize() const { return peerBlockSize(); }
     unsigned int drain(Event *de);
@@ -119,13 +134,7 @@ class DmaDevice : public PioDevice
   public:
     typedef DmaDeviceParams Params;
     DmaDevice(const Params *p);
-    virtual ~DmaDevice();
-
-    const Params *
-    params() const
-    {
-        return dynamic_cast<const Params *>(_params);
-    }
+    virtual ~DmaDevice() { }
 
     void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
                   Tick delay = 0)