O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs

This patch fixes some problems with the drain/switchout functionality
for the O3 cpu and for the ARM ISA and adds some useful debug print
statements.

This is an incremental fix as there are still a few bugs/mem leaks with the
switchout code. Particularly when switching from an O3CPU to a
TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA
I haven't encountered any more assertion failures; now the kernel will
typically panic inside of simulation.

1 files changed, 5 insertions, 4 deletions

diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index 1f2c92425..14d767288 100644
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -44,6 +44,7 @@
 
 #include "base/inet.hh"
 #include "base/trace.hh"
+#include "debug/Drain.hh"
 #include "debug/EthernetAll.hh"
 #include "dev/i8254xGBe.hh"
 #include "mem/packet.hh"
@@ -2072,12 +2073,12 @@ IGbE::drain(Event *de)
     if (tickEvent.scheduled())
         deschedule(tickEvent);
 
-    if (count)
+    if (count) {
+        DPRINTF(Drain, "IGbE not drained\n");
         changeState(Draining);
-    else
+    } else
         changeState(Drained);
 
-    DPRINTF(EthernetSM, "got drain() returning %d", count);
     return count;
 }
 
@@ -2100,12 +2101,12 @@ IGbE::checkDrain()
     if (!drainEvent)
         return;
 
-    DPRINTF(EthernetSM, "checkDrain() in drain\n");
     txFifoTick = false;
     txTick = false;
     rxTick = false;
     if (!rxDescCache.hasOutstandingEvents() &&
         !txDescCache.hasOutstandingEvents()) {
+        DPRINTF(Drain, "IGbE done draining, processing drain event\n");
         drainEvent->process();
         drainEvent = NULL;
     }