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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:08 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:08 -0500 |
| commit | 243223ae638e95cb6744f335010595c4de30d13c (patch) | |
| tree | 536d20b959bc6e31cf60c113c34eaed5064ddb87 /src/dev/ide_ctrl.cc | |
| parent | 999cd8aef5dfa3c22b02b55420608fbb8d7e7822 (diff) | |
| download | gem5-243223ae638e95cb6744f335010595c4de30d13c.tar.xz | |
IDE: Fix issues with new PIIX kernel driver and our model.
The driver can read the IDE config register as a 32 bit register since
some adapters use bit 18 as a disable channel bit. If the size isn't
set in a PRD it should be 64K according to the SPEC (and driver) not
128K.
Diffstat (limited to 'src/dev/ide_ctrl.cc')
| -rw-r--r-- | src/dev/ide_ctrl.cc | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/dev/ide_ctrl.cc b/src/dev/ide_ctrl.cc index a370c7f36..291ce1389 100644 --- a/src/dev/ide_ctrl.cc +++ b/src/dev/ide_ctrl.cc @@ -211,7 +211,10 @@ IdeController::readConfig(PacketPtr pkt) (uint32_t)pkt->get<uint16_t>()); break; case sizeof(uint32_t): - panic("No 32bit reads implemented for this device."); + if (offset == IDEConfig) + pkt->set<uint32_t>(ideConfig); + else + panic("No 32bit reads implemented for this device."); DPRINTF(IdeCtrl, "PCI read offset: %#x size: 4 data: %#x\n", offset, (uint32_t)pkt->get<uint32_t>()); break; @@ -275,7 +278,10 @@ IdeController::writeConfig(PacketPtr pkt) offset, (uint32_t)pkt->get<uint16_t>()); break; case sizeof(uint32_t): - panic("Write of unimplemented PCI config. register: %x\n", offset); + if (offset == IDEConfig) + ideConfig = pkt->get<uint32_t>(); + else + panic("Write of unimplemented PCI config. register: %x\n", offset); break; default: panic("invalid access size(?) for PCI configspace!\n"); @@ -312,6 +318,7 @@ IdeController::writeConfig(PacketPtr pkt) break; case PCI_COMMAND: + DPRINTF(IdeCtrl, "Writing to PCI Command val: %#x\n", config.command); ioEnabled = (config.command & htole(PCI_CMD_IOSE)); bmEnabled = (config.command & htole(PCI_CMD_BME)); break; |